WM8737 datasheet(29/40 Pages) CIRRUS

29 / 40 page

Production Data

WM8737L

PD, Rev 4.4, January 2012

The clocking of the WM8737L is controlled using the CLKDIV2, USB, and SR control bits. Setting the

CLKDIV2 bit divides MCLK by two internally. The USB bit selects between ‘Normal’ and USB mode.

Each combination of the SR4 to SR0 control bits selects one sample rate (see next page). The digital

filter characteristics are automatically adjusted to suit the MCLK and sample rate selected (see Digital

Filter Characteristics).

Since all sample rates are generated by dividing MCLK, their accuracy depends on the accuracy of

MCLK. If MCLK changes, the sample rates change proportionately. Note that some sample rates (e.g.

44.1kHz in USB mode) are approximated, i.e. they differ from their target value by a very small

amount. This is not audible, as the maximum deviation is only 0.27% (48.0214kHz instead of 48kHz

in USB mode - for comparison, a half-tone step corresponds to a 5.9% change in pitch).

In slave mode, it is possible to autodetect the audio clock rate ratio, instead of programming it. The

WM8737L can autodetect the following clock ratios:



CLKDIV2 = 0: MCLK = 128fs, 192fs, 256fs, or 384fs subject to MCLK < 40MHz



CLKDIV2 = 1: MCLK = 256fs, 384fs, 512fs, 768fs, 1024fs, 1536fs, subject to MCLK <

40MHz

MCLK

CLKDIV2=0

MCLK

CLKDIV2=1

ADC SAMPLE RATE

USB

SR [4:0]

FILTER

TYPE

Normal Clock Mode

12.288MHz

24.576MHz

16 kHz (MCLK/768)

01010

24 kHz (MCLK/512)

11100

32 kHz (MCLK/384)

01100

48 kHz (MCLK/256)

00000

96 kHz (MCLK/128) (see Note 1)

01110

11.2896MHz

22.5792MHz

22.05 kHz (MCLK/512)

11010

44.1 kHz (MCLK/256)

10000

88.2 kHz (MCLK/128) (see Note 1)

11110

18.432MHz

36.864MHz

16 kHz (MCLK/1152)

01011

24 kHz (MCLK/768)

11101

32 kHz (MCLK/576)

01101

48 kHz (MCLK/384)

00001

96 kHz (MCLK/192) (see Note 1)

01111

16.9344MHz

33.8688MHz

22.05 kHz (MCLK/768)

11011

44.1 kHz (MCLK/384)

10001

88.2 kHz (MCLK/192) (see Note 1)

11111

USB Mode

12.000MHz

24.000MHz

16 kHz (MCLK/750)

01010

22.0588 kHz (MCLK/544)

11011

24 kHz (MCLK/500)

11100

32 kHz (MCLK/375)

01100

44.118 kHz (MCLK/272)

10001

48 kHz (MCLK/250)

00000

88.235 kHz (MCLK/136) (see Note 1)

11111

96 kHz (MCLK/125)

01110

Table 16 Master Clock and Sample Rates

Note 1: The 3D enhancement is not supported at sample frequencies of 88.2kHz, 88.235kHz,

and 96kHz. When using these sample frequencies the 3D enhancement function

should be bypassed by first setting register R13 (0Dh) to 1_110x_xxxx (1C0h), where

x_xxxx represents the required values for the ALC in the application, and then setting

Note that the above sequence uses test bits that are not documented and the use of

these test bits, other than as described above, is not recommended and is not

supported.

WM8737 Datasheet(PDF) 29 Page - Cirrus Logic

WM8737 Datasheet(HTML) 29 Page - Cirrus Logic

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40

Datasheet Download

Link URL