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CS48520 Datasheet(PDF) 12 Page - Cirrus Logic

Part # CS48520
Description  Cost-effective, High-performance 32-bit DSP
PDF  23 Pages
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Manufacturer  CIRRUS [Cirrus Logic]
Direct Link  http://www.cirrus.com
Logo CIRRUS - Cirrus Logic

CS48520 Datasheet(HTML) 12 Page - Cirrus Logic

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12
DS734F5
5.9 Switching Characteristics—Serial Control Port–SPI Slave Mode
5.9 Switching Characteristics—Serial Control Port–SPI Slave Mode
Figure 5-3. Serial Control Port–SPI Slave Mode Timing
Internal DCLK period1
DCLKP
ns
CS4852x-CQZ
CS4854x-CQZ
CS4856x-CQZ
CS4854x-DQZ
CS4856x-DQZ
6.7
6.7
6.7
6.7
6.7
1/Fxtal
1/Fxtal
1/Fxtal
1/Fxtal
1/Fxtal
1.After initial power-on reset, Fdclk = Fxtal. After initial kick-start commands, the PLL is locked to max Fdclk and remains locked until the next power-on
reset.
Parameter
Symbol
Min
Typical
Max
Units
SCP_CLK frequency1
1.The specification fspisck indicates the maximum speed of the hardware. The system designer should be aware that the actual maximum speed of the
communication port may be limited by the firmware application. Flow control using the SCP_BSY# pin should be implemented to prevent overflow of
the input data buffer. At boot the maximum speed is Fxtal/3.
fspisck
——
25
MHz
SCP_CS# falling to SCP_CLK rising
tspicss
24
ns
SCP_CLK low time
tspickl
20
ns
SCP_CLK high time
tspickh
20
ns
Setup time SCP_MOSI input
tspidsu
5—
ns
Hold time SCP_MOSI input
tspidh
5—
ns
SCP_CLK low to SCP_MISO output valid
tspidov
——
11
ns
SCP_CLK falling to SCP_IRQ# rising
tspiirqh
20
ns
SCP_CS# rising to SCP_IRQ# falling
tspiirql
0—
ns
SCP_CLK low to SCP_CS# rising
tspicsh
24
ns
SCP_CS# rising to SCP_MISO output high-Z
tspicsdz
—20
ns
SCP_CLK rising to SCP_BSY# falling
tspicbsyl
—3*DCLKP+20
ns
Parameter
Symbol
Min
Max
Unit
SCP_BSY#
SCP_CS#
SCP_CLK
SCP_MOSI
SCP_MISO
SCP_IRQ#
0
12
670
56
7
tspicss
tspickl
tspickh
tspidsu
tspidh
tspidov
A6
A5
A0
R/W
MSB
LSB
MSB
LSB
tspicsh
tspibsyl
tspiirql
tspiirqh
fspisck
tspicsdz



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