WM8232 datasheet(15/141 Pages) CIRRUS

15 / 141 page

WM8232

Rev 4.6

Test Conditions

AVDD = LDOVDD = DBVDD = 3.3V, AGND = LDOGND = DBGND= 0V, TA = 25C, MCLK= 35MHz unless otherwise stated.

PARAMETER

SYMBOL

TEST CONDITIONS

MIN

TYP

MAX

UNITS

MCLK cycle period (see note 2)

tPER

28.6

200

MCLK high period (see note 2)

tMCLKH

0.4 * tPER

0.5*tPER

0.6 * tPER

MCLK low period (see note 2)

tMCLKL

0.4 * tPER

0.5*tPER

0.6 * tPER

MCLK rising edge to DLL tap 0

tMCLKD

Aperture delay

(from RSMP falling edge)

tRSMPD

Aperture delay

(from VSMP falling edge)

tVSMPD

RSMP high period

tRSMPH

VSMP high period

tVSMPH

28 *

tPER/60

RSMP falling edge to VSMP rising edge

tRV

0.5

VSMP falling edge to RSMP rising edge

tVR

0.5

Output data latency

(from 1st falling edge of VSMP)

LAT

LVDS 10-bit 5pair mode

clock

LVDS 10-bit 3pair mode,

CMOS 10-bit output mode

clock

Other output modes

clock

Notes:

1clock = tPER (MCLK cycle period)

MCLK cycle period and MCLK high/low period are measured at 50% of the respective rising/falling edges

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

R130 (82h)

RSMP rise

5:0

RSMP_RISE[5:0]

01_1100

RSMP rise edge (0 to 59)

R131 (83h)

RSMP fall

5:0

RSMP_FALL[5:0]

10_0110

RSMP fall edge (0 to 59)

R132 (84h)

VSMP rise

5:0

VSMP_RISE[5:0]

00_1000

VSMP rise edge (0 to 59)

R133 (85h)

VSMP fall

5:0

VSMP_FALL[5:0]

10_1000

VSMP fall edge (0 to 59)

WM8232 Datasheet(PDF) 15 Page - Cirrus Logic

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