LP5910 datasheet(17/34 Pages) TI1

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CIN

COUT

OUT

GND

Via

Time (µs)

-25

100

125

150

0.5

1.5

2.5

D021

VIN

VOUT

Time (µs)

-20

-10

-12

-8

-4

100

120

D022

IOUT

'VOUT

LP5910

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SNVSA91E – SEPTEMBER 2015 – REVISED JULY 2017

Product Folder Links: LP5910

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8.2.3 Application Curves

VEN = VIN

VOUT = 1.8 V

COUT = 1 µF

Figure 26. Turnon Time

VIN = 2.3 V

VOUT = 1.8 V

COUT = 1 µF

IOUT = 1 mA to 100 mA

tRISE = 10 µs

Figure 27. Load Transient Response

9 Power Supply Recommendations

This device is designed to operate from an input supply voltage range of 1.3 V to 3.3 V. The input supply must

be well regulated and free of spurious noise. To ensure that the LP5910 output voltage is well regulated and

dynamic performance is optimum, the input supply must be at least VOUT + 0.5 V.

10 Layout

10.1 Layout Guidelines

The dynamic performance of the LP5910 is dependant on the layout of the PCB. PCB layout practices that are

adequate for typical LDOs may degrade the PSRR, noise, or transient performance of the LP5910.

Best performance is achieved by placing CIN and COUT on the same side of the PCB as the LP5910 device, and

as close as is practical to the package. The ground connections for CIN and COUT must be back to the LP5910

GND pin using as wide and as short of a copper trace as is practical.

Avoid connections using long trace lengths, narrow trace widths, and/or connections through vias. These add

parasitic inductances and resistance that results in inferior performance especially during transient conditions.

10.2 Layout Examples

Figure 28. LP5910 Typical DSBGA Layout

LP5910 Datasheet(PDF) 17 Page - Texas Instruments

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