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RT2856 Datasheet(PDF) 13 Page - Richtek Technology Corporation

Part # RT2856
Description  Synchronous Step-Down Converter
PDF  19 Pages
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Manufacturer  RICHTEK [Richtek Technology Corporation]
Direct Link  http://www.richtek.com
Logo RICHTEK - Richtek Technology Corporation

RT2856 Datasheet(HTML) 13 Page - Richtek Technology Corporation

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RT2856
13
DS2856-10
October 2016
www.richtek.com
©
Copyright
2016 Richtek Technology Corporation. All rights reserved.
is a registered trademark of Richtek Technology Corporation.
SS
REF
SS
SS
CV
T
=
I
(2)
where CSS is the external soft-start capacitor, ISS is the
soft-start charge current (2
μA), VREF is the feedback
reference voltage (0.8V).
Once the input voltage falls below UVLO threshold, the
EN pin is pulled low, or the OTP is triggered, the device
stops switching and the SS/TR pin starts to discharge. It
is held such shutdown condition until the event is cleared
and the SS/TR pin has already discharged to ground
ensuring proper soft-start behavior.
During the pre-biased start-up sequence, the output of
device is not discharged by low-side power switch
because the device is designed to prevent low-side
MOSFET sinking. It is allowed to sink when the SS/TR
pin exceeds 2.1V.
Slope Compensation
Slope compensation provides stability in constant
frequency architectures by preventing sub-harmonic
oscillations at duty cycles greater than 50%. It is
accomplished internally by adding a compensating ramp
to the inductor current signal. Normally, the peak inductor
current is remained constant under the whole duty cycle
range when slope compensation is added. For the device,
Figure 2. Enable Timing Control
An external MOSFET can be added to implement digital
control from the EN pin to ground, as shown in Figure 3.
In this case, there is no need to connect a pull-up resistor
between the VIN and EN pins since the EN pin is pulled
up by the internal current source. The device can simply
achieve the digital control only through an external
MOSFET on EN pin.
RT2856
EN
GND
External
Digital Control
VIN
VIN
Figure 3. Digital Enable Control
The EN pin can also be applied to adjust its Under-Voltage
Lockout (UVLO) threshold with two external resistors
divider from the both input VIN and PVIN pins used together
or separately, and the application structures can refer to
Figure 4, Figure 5, and Figure 6.
RT2856
EN
GND
VIN
REN
CEN
VIN
separated inductor current signal is used to monitor over-
current condition, so the maximum output current stays
relatively constant regardless of duty cycle. More
discussions about over-current protection are described
in a later section.
Enable Operation
The EN pin is an device enable input. Pulling the EN pin
to logic low that is typically less than the set threshold
voltage 1.17V, the device shuts down and enters to low
quiescent current state about 2
μA. The regulator starts
switching again once the EN pin voltage exceeds the
threshold voltage 1.21V. In additional, the EN pin is
implemented with an internal pull-up current source which
allows to enable the device when the EN pin is floating.
For general external timing control, the EN pin can be
externally pulled high by adding a capacitor and a resistor
from the VIN pin as Figure 2.



OUT
REF
R1
V
= V
1
R2
For high efficiency, the divider resistance must adopt larger
values, but too large values may induce noises and voltage
errors by the coupled FB pin input current. It is
recommended to use the values between 10k
Ω and
100k
Ω. The output voltage is set by an external resistive
voltage divider according to the following Equation (1) :
(1)
where VREF is the feedback reference voltage (0.8V typ.).
Soft-Start
The device contains an external soft-start clamp that
gradually raises the output voltage. The soft-start timing
is programmed by the external capacitor between SS/TR
pin and GND. The device provides an internal 2
μA charge
current for the external capacitor. If a 10nF capacitor is
used to set the soft-start, the period can be 4ms. The
calculations for external charge capacitor CSS and soft-
start time TSS are shown in Equation (2) :



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