Tester channel

Device pin

output under test

21

DLP650NE

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DLPS097 – AUGUST 2017

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Window Characteristics (continued)

CONDITIONS

MIN

NOM

MAX

UNIT

(3)

See the TI application report Wavelength Transmittance Considerations for DLP® DMD Window, .

(4)

Angle of incidence 0° to 45° at 420 nm to 680 nm. Double pass system. Two AR coating surfaces at 0.5% reflectivity per AR coating up

to 30° AOI.

Window transmittance,

single–pass through both

angles between 0 AOI and 30 AOI (single pass) over the

wavelength range (between 420 nm and 680 nm)

97%

Average Window Transmittance Tave measured at all

angles 0 – 30 AOI (single pass) over the wavelength

99%

Average Window Transmittance Tave measured at all

angles 30 – 45 AOI (single pass) over the wavelength

range (420nm – 680nm)

97%

6.12 Chipset Component Usage Specification

The DLP650NE is a component of one or more DLP chipsets. Reliable function and operation of the DLP650NE

requires that it be used in conjunction with the other components of the applicable DLP chipset, including those

components that contain or implement TI DMD control technology. TI DMD control technology are the TI

technology and devices for operating or controlling a DLP DMD.

7 Parameter Measurement Information

Figure 12 shows an equivalent test load circuit for the output under test. The load capacitance value stated is

only for characterization and measurement of AC timing signals. This load capacitance value does not indicate

the maximum load the device is capable of driving.

Timing reference loads are not intended as a precise representation of any particular system environment or

depiction of the actual load presented by a production test. Use IBIS or other simulation tools to correlate the

timing reference load to a system environment. Refer to the Application and Implementation section.

Figure 12. Test Load Circuit