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DLP650NE

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DLPS097 – AUGUST 2017

Product Folder Links: DLP650NE

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Copyright © 2017, Texas Instruments Incorporated

(1)

All voltages are referenced to common ground VSS. Supply voltages VCC, VCCI, VOFFSET, VBIAS, and VRESET are all required for

proper DMD operation. VSS must also be connected.

(2)

Applies to LVCMOS input pins only. Does not apply to LVDS pins and MBRST pins.

(3)

LVCMOS input pins utilize an internal 18000 Ω passive resistor for pull-up and pull-down configurations. Refer to Pin Configuration and

Functions to determine pull-up or pull-down configuration used.

(4)

To prevent excess current, the supply voltage change |VCCI – VCC| must be less than specified limit.

(5)

To prevent excess current, the supply voltage change |VBIAS – VOFFSET| must be less than specified limit.

6.6 Electrical Characteristics

over operating free-air temperature range (unless otherwise noted)

PARAMETER

MIN

TYP

MAX

UNIT

High-level output voltage

2.4

V

Low -level output voltage

0.4

V

250

µA

Low-level input current

–250

µA

High–impedance output current

VCC = 3.45 V

10

µA

CURRENT

VCC = 3.45 V

1100

mA

VCCI = 3.45 V

500

VOFFSET = 8.75 V

25

mA

VBIAS = 16.5 V

14

Supply current

VRESET = –10.5 V

11

mA

Total Sum

1650

CAPACITANCE

Input capacitance

ƒ = 1 MHz

10

pF

Output capacitance

ƒ = 1 MHz

10

pF

Reset group capacitance

MBRST(14:0)

ƒ = 1 MHz

all inputs interconnected,

(1920 x 1080) array

330

390

pF