LP5569 datasheet(49/86 Pages) TI1

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LP5569

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SNVSAP8 – JULY 2017

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Table 26. LED8_CONTROL Register Field Descriptions (continued)

Bit

Field

Type

Reset

Description

1–0

RESERVED

R/W

8.6.1.13 LED0_PWM Register (Address = 16h) [reset = 0h]

LED0_PWM is shown in Figure 32 and described in Table 27.

Return to Summary Table.

This is the PWM duty cycle control for the LED0 output.

Figure 32. LED0_PWM Register

pwm0

R/W-0h

Table 27. LED0_PWM Register Field Descriptions

Bit

Field

Type

Reset

Description

7–0

pwm0

R/W

00h = 0% duty cycle (default)

80h = 50% duty cycle

FFh = 100% duty cycle

8.6.1.14 LED1_PWM Register (Address = 17h) [reset = 0h]

LED1_PWM is shown in Figure 33 and described in Table 28.

Return to Summary Table.

This is the PWM duty cycle control for the LED1 output.

Figure 33. LED1_PWM Register

pwm1

R/W-0h

Table 28. LED1_PWM Register Field Descriptions

Bit

Field

Type

Reset

Description

7–0

pwm1

R/W

00h = 0% duty cycle (default)

80h = 50% duty cycle

FFh = 100% duty cycle

8.6.1.15 LED2_PWM Register (Address = 18h) [reset = 0h]

LED2_PWM is shown in Figure 34 and described in Table 29.

Return to Summary Table.

This is the PWM duty cycle control for the LED2 output.

Figure 34. LED2_PWM Register

pwm2

R/W-0h

LP5569 Datasheet(PDF) 49 Page - Texas Instruments

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