LP5569 datasheet(51/86 Pages) TI1

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LP5569

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SNVSAP8 – JULY 2017

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Table 32. LED5_PWM Register Field Descriptions

Bit

Field

Type

Reset

Description

7–0

pwm5

R/W

00h = 0% duty cycle (default)

80h = 50% duty cycle

FFh = 100% duty cycle

8.6.1.19 LED6_PWM Register (Address = 1Ch) [reset = 0h]

LED6_PWM is shown in Figure 38 and described in Table 33.

Return to Summary Table.

This is the PWM duty cycle control for the LED6 output.

Figure 38. LED6_PWM Register

pwm6

R/W-0h

Table 33. LED6_PWM Register Field Descriptions

Bit

Field

Type

Reset

Description

7–0

pwm6

R/W

00h = 0% duty cycle (default)

80h = 50% duty cycle

FFh = 100% duty cycle

8.6.1.20 LED7_PWM Register (Address = 1Dh) [reset = 0h]

LED7_PWM is shown in Figure 39 and described in Table 34.

Return to Summary Table.

This is the PWM duty cycle control for the LED7 output.

Figure 39. LED7_PWM Register

pwm7

R/W-0h

Table 34. LED7_PWM Register Field Descriptions

Bit

Field

Type

Reset

Description

7–0

pwm7

R/W

00h = 0% duty cycle (default)

80h = 50% duty cycle

FFh = 100% duty cycle

8.6.1.21 LED8_PWM Register (Address = 1Eh) [reset = 0h]

LED8_PWM is shown in Figure 40 and described in Table 35.

Return to Summary Table.

This is the PWM duty cycle control for the LED8 output.

Figure 40. LED8_PWM Register

pwm8

R/W-0h

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