TPIC5401

H-BRIDGE GATE-PROTECTED

POWER DMOS ARRAY

SLIS024A – DECEMBER 1993 – REVISED MARCH 1994

4

POST OFFICE BOX 655303

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

td(on)

Turn-on delay time

32

65

td(off)

Turn-off delay time

VDD = 25 V,

RL = 25 Ω,ten = 10 ns,

40

80

ns

tr

Rise time

DD

,

t dis = 10 ns,

L

,

See Figure 2

en

,

15

30

ns

tf

Fall time

25

50

Qg

Total gate charge

V48 V

I1 A

V10 V

6.6

8

Qgs(th) Threshold gate-to-source charge

VDS = 48 V,

See Figure 3

ID = 1 A,

VGS = 10 V,

0.8

1

nC

Qgd

Gate-to-drain charge

See Figure 3

2.6

3.2

Ld

Internal drain inductance

5

nH

Ls

Internal source inductance

5

nH

Rg

Internal gate resistance

0.25

Ω

thermal resistances

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

R

θJA

Junction to ambient thermal resistance (see Note 4)

DW

90

R

θJA

Junction-to-ambient thermal resistance (see Note 4)

NE

60

R

θJB

Junction-to-board thermal resistance

DW

All outputs with equal power

53

°C/W

R

θJP

Junction to pin thermal resistance

DW

30

R

θJP

Junction-to-pin thermal resistance

NE

25

NOTE 4: Package mounted on an FR4 printed-circuit board with no heatsink.

PARAMETER MEASUREMENT INFORMATION

IRM†

Reverse di/dt = 100 A/

µs

trr(SD)

† IRM = maximum recovery current

25% of IRM†

VDS = 48 V

VGS = 0

TJ = 25°C

Z1 and Z3‡

Time – ns

2

1

0

– 1

– 2

– 3

– 4

0

200

400

600

800

1000

1200

Shaded Area = QRR

‡ The above waveform is representative of Z2, Z4, D1, and D2 in shape only.

Figure 1. Reverse-Recovery-Current Waveform of Source-to-Drain Diode