WM9709

Production Data

w

PD Rev 1.3 February 2003

6

CLOCK SPECIFICATIONS

BITCLK

SYNC

t

CLK_HIGH

t

CLK_LOW

t

CLK_PERIOD

t

SYNC_HIGH

t

SYNC_LOW

t

SYNC_PERIOD

Figure 2 Clock Specifications (50pF External Load)

Note: Worst case duty cycle restricted to 40/60.

PARAMETER

SYMBOL

MIN

TYP

MAX

UNIT

BITCLK frequency

12.288

MHz

BITCLK period

81.4

ns

BITCLK output jitter

750

ps

BITCLK high pulse width

32.56

40.7

48.84

ns

BITCLK low pulse width

32.56

40.7

48.84

ns

SYNC frequency

48.0

kHz

SYNC period

20.8

µs

SYNC high pulse width

1.3

µs

SYNC low pulse width

19.5

µs

DATA OUTPUT AND INPUT TIMES

BITCLK

SYNC,

SDATAOUT,

SDATAIN

t

CO

t

SETUP

t

HOLD

Figure 3 Data Output and Input Timing

PARAMETER

SYMBOL

MIN

TYP

MAX

UNIT

Setup to falling edge of BITCLK

10.0

ns

Hold from falling edge of

BITCLK

10.0

ns

Output Valid Delay from rising

edge of BITCLK

15.0

ns

ATE IN CIRCUIT TEST MODE

When the WM9709 is placed in the ATE test mode, its digital AC-link outputs (BITCLK and

SDATAIN) are driven to a high impedance state. This allows ATE in circuit testing of the WM9709.