WM9709

Production Data

w

PD Rev 1.3 February 2003

10

SYNC is fixed at 48 kHz, and is derived by the AC-link controller which divides down the serial clock

(BITCLK). BITCLK, fixed at 12.288 MHz, provides the necessary clocking granularity to support 12,

20-bit outgoing and incoming time slots. AC-link serial data is transitioned on each rising edge of

BITCLK. The receiver of AC-link data, (WM9709 for SDATAOUT data), samples each serial bit on

the falling edges of BITCLK.

The AC-link protocol provides for a special 16-bit time slot (slot 0) wherein each bit conveys a valid

tag for its corresponding time slot within the current audio frame. A ‘1’ in a given bit position of slot 0

indicates that the corresponding time slot within the current audio frame has been assigned to a data

stream, and contains valid data. If a slot is “tagged” invalid, WM9709 will ignore the corresponding

data slot.

SYNC remains high for a total duration of 16 BITCLKs at the beginning of each audio frame.

The portion of the audio frame where SYNC is high is defined as the “Tag Phase”. The remainder of

the audio frame where SYNC is low is defined as the “Data Phase”. Additionally, for power savings,

all clock, sync, and data signals can be halted.

AC-LINK AUDIO OUTPUT FRAME (SDATAOUT)

SDATAOUT, the audio frame data input to the WM9709, contains audio and control data time

multiplexed onto one bus. As briefly mentioned earlier, each audio output frame supports up to 12,

20-bit outgoing data time slots. Slot 0 is a special reserved time slot containing 16-bits, which are

used for AC-link protocol infrastructure.

The first bit within slot 0 is a global bit (SDATAOUT slot 0, bit 15) which flags the validity for the

entire audio frame. If the “Valid Frame” bit is a 1, this indicates that the current audio frame contains

at least one time slot of valid data. The next 12-bit positions sampled by the WM9709 indicate which

of the corresponding 12 time slots contain valid data.

SYNC

BITCLK

SDATAOUT

WM9709 samples SYNC assertion here

WM9709 samples first

SDATAOUT bit of frame here

End of previous Audio Frame

Valid

Frame

Slot (1)

Slot (2)

Figure 9 Start of an Audio Output Frame

A new audio output frame begins with a low to high transition of SYNC as shown in Figure 7. SYNC

is synchronous to the rising edge of BITCLK. On the immediately following falling edge of BITCLK,

WM9709 samples the assertion of SYNC. This falling edge marks the time when both sides of the

AC-link are aware of the start of a new audio frame. On the next rising edge of BITCLK, the AC-link

controller transitions SDATAOUT into the first bit position of slot 0 (“Valid Frame” bit). Each new bit

position is presented to AC-link on a rising edge of BITCLK, and subsequently sampled by the

WM9709 on the following falling edge of BITCLK. This sequence ensures that data transitions and

subsequent sample points for both incoming and outgoing data streams are time aligned.

Baseline AC’97 specified audio functionality MUST ALWAYS sample rate convert to and from a

fixed 48 kS/s on the AC’97 controller.

This requirement is necessary to ensure that interoperability between the AC-link controller and

WM9709 can be guaranteed by definition for baseline specified AC’97 features.

SDATAOUT’s composite stream is MSB justified (MSB first) with all non-valid slot bit positions

stuffed with 0s by the AC-link controller.

As an example, consider an 8-bit sample stream that is being played out to one of WM9709’s DACs.

The first 8-bit positions are presented to the DAC (MSB justified) followed by the next 12-bit-

positions, which are stuffed with 0s by the AC-link controller. This ensures that regardless of the

resolution of the implemented DAC (16, 18 or 20-bit), the least significant bits will introduce no DC

biasing.