Z85233 datasheet(13/317 Pages) ZILOG

13 / 317 page

SCC™/ESCC™ User’s Manual

General Description

1-3

The Z85C30 CMOS SCC has added new features, while

maintaining 100% hardware/software compatibility. It has

the following new features:

New programmable WR7' (write register 7 prime) to

enable new features.

Improvements to support SDLC mode of synchronous

communication:

–

Improved functionality to ease sending back-to

back frames

–

Automatic SDLC opening Flag transmission*

–

Automatic Tx Underrun/EOM Latch reset in SDLC

mode*

–

Automatic /RTS deactivation*

–

TxD pin forced “H” in SDLC NRZI mode after

closing ﬂag*

–

Complete CRC reception*

–

Improved response to Abort sequence in status

FIFO

–

Automatic Tx CRC generator preset/reset

–

Extended read for write registers*

–

Write data setup timing improvement

Improved AC timing:

–

Three to 3.5 PCLK access recovery time.

–

Programmable /DTR//REQ timing*

–

Elimination of write data to falling edge of /WR

setup time requirement

–

Reduced /INT timing

Other features include:

–

Extended read function to read back the written

value to the write registers*

–

Latching RR0 during read

–

RR0, bit D7 and RR10, bit D6 now has reset

defaultvalue.

Some of the features listed above are available by de-

fault, and some of them (features with “*”) are disabled on

default.

ESCC (Enhanced SCC) is pin and software compati-

ble to the CMOS version, with the following additional

enhancements.

Deeper transmit FIFO (4 bytes)

Deeper receive FIFO (8 bytes)

Programmable FIFO interrupt and DMA request level

Seven enhancements to improve SDLC link layer

supports:

–

Automatic transmission of the opening ﬂag

–

Automatic reset of Tx Underrun/EOM latch

–

Deactivation of /RTS pin after closing ﬂag

–

Automatic CRC generator preset

–

Complete CRC reception

–

TxD pin automatically forced high with NRZI

encoding when using mark idle

–

Status FIFO handles better frames with an

ABORT

–

Receive FIFO automatically unlocked for special

receive interrupts when using the SDLC status

FIFO

Delayed

bus

latching

for

easier

microprocessor

interface

New programmable features added with Write Register

7' (WR seven prime)

Write registers 3, 4, 5 and 10 are now readable

Read register 0 latched during access

DPLL counter output available as jitter-free transmitter

clock source

Enhanced /DTR, /RTS deactivation timing

UM010901-0601

Z85233 Datasheet(PDF) 13 Page - Zilog, Inc.

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