Z85233 datasheet(69/317 Pages) ZILOG

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SCC™/ESCC™ User’s Manual

SCC/ESCC Ancillary Support Circuitry

3-8

3.4 DPLL DIGITAL PHASE-LOCKED LOOP (Continued)

3.4.1 DPLL Operation in the NRZI Mode

To operate in NRZI mode, the DPLL must be supplied with

a clock that is 32 times the data rate. The DPLL uses this

clock, along with the receive data, to construct receive and

transmit clock outputs that are phased to properly receive

and transmit data.

To do this, the DPLL divides each bit cell into four regions,

and makes an adjustment to the count cycle of the 5-bit

counter dependent upon the region a transition on the re-

ceive data input occurred (Figure 3-6).

Ordinarily, a bit-cell boundary occurs between count 15

and count 16, and the DPLL output causes the data to be

sampled in the middle of the bit cell. However, four differ-

ent situations can occur:

If the bit-cell boundary (from space to mark) occurs any-

where during the second half of count 15 or the first half of

count 16, the DPLL allows the transition without making a

correction to its count cycle.

If the bit cell boundary (from space to mark) occurs be-

tween the middle of count 16 and count 31, the DPLL is

sampling the data too early in the bit cell. In response to

this, the DPLL extends its count by one during the next 0

to 31 counting cycle, which effectively moves the edge of

the clock that samples the receive data closer to the center

of the bit cell.

If the transition occurs between count 0 and the middle of

count 15, the output of the DPLL is sampling the data too

late in the bit cell. To correct this, the DPLL shortens its

count by one during the next 0 to 31 counting cycle, which

effectively moves the edge of the clock that samples the

receive data closer to the center of the bit cell.

If the DPLL does not see any transition during a counting cy-

cle, no adjustment is made in the following counting cycle.

If an adjustment to the counting cycle is necessary, the

DPLL modifies count 5, either deleting it or doubling it.

Thus, only the Low time of the DPLL output is lengthened

or shortened.

While the DPLL is in search mode, the counter remains at

count 16, where the DPLL outputs are both High. The

missing clock latches in the DPLL, which may be accessed

in RR10, are not used in NRZI mode. An example of the

DPLL in operation is shown in Figure 3-7.

Figure 3-6. DPLL in NRZI Mode

18 19 20

21 22 23 24 25 26 27 28 29 30 31

2345

789

12 13 14

No Change

Bit Cell

Count

Correction

DPLL Out

Add One Count

Subtract One Count

UM010901-0601

Z85233 Datasheet(PDF) 69 Page - Zilog, Inc.

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