VREG

213_VCC

GND

RSTN

RSTN

L/CD

GND

GND

EQ

EQ

SCLKD

C3

0.1 µF

C2

0.1 µF

C1

18

TUSB213-Q1

SLLSF06 – SEPTEMBER 2017

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Product Folder Links: TUSB213-Q1

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Copyright © 2017, Texas Instruments Incorporated

10 Layout

10.1 Layout Guidelines

To avoid the need for signal vias, it is highly recommend to route the High Speed traces on the same surface

layer than the TUSB213-Q1 is placed. shows an example how one could layout the PCB for TUSB213-Q1.

The layout should use impedance controlled traces to maintain 90 Ω differential impedance for the whole signal

path as required per USB 2.0 specification. General guidelines for highspeed signal routing apply.

10.2 Layout Example

Figure 22. Layout Example