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LM9800CCV Datasheet(PDF) 8 Page - National Semiconductor (TI) |
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LM9800CCV Datasheet(HTML) 8 Page - National Semiconductor (TI) |
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8 / 34 page  Pin Descriptions (Continued) V TEST1, V TEST2 Analog Inputs/Outputs. These pins are used for testing the device during manufacture and should be left unconnected. Configuration Register I/O SDI Digital Input. Serial Data Input pin. SDO Digital Output. Serial Data Output pin. SCLK Digital Input. This is the serial data clock, used to clock data in through SDI and out through SDO. SCLK is asynchronous to MCLK. Input data is latched and output data is changed on the rising edge of SCLK. CS Digital Input. This is the Chip Select signal for writing to the Configuration Register through the serial interface. This input must be low in order to communicate with the Configuration Register. This pin is used for serial I/O only–it has no effect on any other section of the chip. Note: The SYNC pin must be high to read or write from the Configuration register. General Digital I/O MCLK Digital Input. This is the 20 MHz (typical) master system clock. SYNC Digital Input. A low-to-high transition on this input begins a line scan operation. The line scan operation terminates when this input is taken low. A low-to-high transition on this input will also reset the serial I/O port to the Configuration Register. The SYNC pin must be high to read or write from the Configuration register. Digital Coefficient I/O CD0 (LSB)– CD6 (MSB) Digital Inputs. Correction Coefficient Databus. This is the 7-bit data path for the gain adjust PGA, used during line scan. CCLK Digital Output. This is the signal that is used to clock the Gain coefficients into the LM9800. Data is latched on the rising edge of CCLK. Digital Output I/O DD0 (LSB)– DD7 (MSB) Digital Outputs. Pixel Output Databus. This data bus outputs the 8-bit digital output data during line scan. EOC Digital Output. This is the End of Conversion signal from the ADC indicating that new pixel data is available. RD Digital Input. Taking this input low places the data stored in the output latch on the bus. When this input is high the DD0–DD7 bus is in TRI-STATE. Analog Power V A This is the positive supply pin for the analog supply. It should be connected to a voltage source of +5V and bypassed to AGND with a 0.1 µF monolithic capacitor in parallel with a 10 µF tantalum capacitor. AGND This is the ground return for the analog supply. Digital Power V D This is the positive supply pin for the digital supply. It should be connected to a voltage source of +5V and bypassed to DGND with a 0.1 µF monolithic capacitor. DGND This is the ground return for the digital supply. V D(I/O) This is the positive supply pin for the digital supply for the LM9800’s I/O. It should be connected to a voltage source of +3V to +5V and bypassed to DGND (I/O) with a 0.1 µF monolithic capacitor. If the supply for this pin is different than the supply for V A and VD, it should also be bypassed with a 10 µF tantalum capacitor. DGND (I/O) This is the ground return for the digital supply for the LM9800’s I/O. www.national.com 8 |
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