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LTC3703

3703f

appropriate breakdown specification. Since many high

voltage MOSFETs have higher threshold voltages (typi-

cally, VGS(MIN) ≥ 6V), the LTC3703 is designed to be used

with a 9V to 15V gate drive supply (DRVCC pin).

For maximum efficiency, on-resistance RDS(ON) and input

capacitance should be minimized. Low RDS(ON) minimizes

conduction losses and low input capacitance minimizes

transition losses. MOSFET input capacitance is a combi-

nation of several components but can be taken from the

typical “gate charge” curve included on most data sheets

(Figure 9).

The curve is generated by forcing a constant input current

into the gate of a common source, current source loaded

stage and then plotting the gate voltage versus time. The

initial slope is the effect of the gate-to-source and the gate-

to-drain capacitance. The flat portion of the curve is the

result of the Miller multiplication effect of the drain-to-gate

capacitance as the drain drops the voltage across the

current source load. The upper sloping line is due to the

drain-to-gate accumulation capacitance and the gate-to-

source capacitance. The Miller charge (the increase in

coulombs on the horizontal axis from a to b while the curve

is flat) is specified for a given VDS drain voltage, but can be

adjusted for different VDS voltages by multiplying by the

ratio of the application VDS to the curve specified VDS

values. A way to estimate the CMILLER term is to take the

change in gate charge from points a and b on a manufac-

turers data sheet and divide by the stated VDS voltage

specified. CMILLER is the most important selection criteria

for determining the transition loss term in the top MOSFET

but is not directly specified on MOSFET data sheets. CRSS

and COS are specified sometimes but definitions of these

parameters are not included.

When the controller is operating in continuous mode the

duty cycles for the top and bottom MOSFETs are given by:

APPLICATIO S I FOR ATIO

MainSwitchDutyCycle

SynchronousSwitchDutyCycle

OUT

–

The power dissipation for the main and synchronous

MOSFETs at maximum output current are given by:

MAIN

MAX

DR ON

OUT

MAX

MILLER

TH IL

SYNC

MAX

DS N





























= 







–

()

–

()(

)•

–

()

–

() ()

()

where

δ is the temperature dependency of RDS(ON), RDR is

the effective top driver resistance (approximately 2

Ω at

VGS = VMILLER), VIN is the drain potential and the change

in drain potential in the particular application. VTH(IL) is the

data sheet specified typical gate threshold voltage speci-

fied in the power MOSFET data sheet at the specified drain

current. CMILLER is the calculated capacitance using the

gate charge curve from the MOSFET data sheet and the

technique described above.

Both MOSFETs have I2R losses while the topside N-channel

equation includes an additional term for transition losses,

which peak at the highest input voltage. For VIN < 25V, the

high current efficiency generally improves with larger

MOSFETs, while for VIN > 25V, the transition losses

rapidly increase to the point that the use of a higher

RDS(ON)devicewithlowerCMILLERactuallyprovideshigher

efficiency. The synchronous MOSFET losses are greatest

at high input voltage when the top switch duty factor is low

or during a short circuit when the synchronous switch is

on close to 100% of the period.

The term (1 +

δ) is generally given for a MOSFET in the

form of a normalized RDS(ON) vs temperature curve, and

typically varies from 0.005/

°C to 0.01/°C depending on

the particular MOSFET used.

Figure 9. Gate Charge Characteristic

–

VDS

VIN

VGS

MILLER EFFECT

QIN

CMILLER = (QB – QA)/VDS

VGS

–

3703 F09

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