AD9234 datasheet(63/67 Pages) AD

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AD9234

Data Sheet

Reg

Addr

(Hex)

Name

Bit 7

(MSB)

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0 (LSB)

Default

Notes

0x572

JESD204B

Link Mode

Control 2

SYNCINB± pin control

00 = normal

10 = ignore SYNCINB±

(force CGS)

11 = ignore SYNCINB±

(force ILAS/user data)

SYNC-

INB± pin

invert

0 = active

low

1 = active

high

SYNCINB±

pin type

0 =

differential

1 = cmos

8B/10B

bypass

0 = normal

1 = bypass

8B/10B bit

invert

0 = normal

1 = invert

the a…j

symbols

0x00

0x573

JESD204B

Link Mode

Control 3

CHKSUM mode

00 = sum of all 8-bit

link config registers

01 = sum of individual

link config fields

10 = checksum set to

zero

Test injection point

00 = N΄ sample input

01 = 10-bit data at

8B/10B output (for

PHY testing)

10 = 8-bit data at

scrambler input

JESD204B test mode patterns

0000 = normal operation (test mode disabled)

0001 = alternating checker board

0010 = 1/0 word toggle

0011 = 31-bit PN sequence—X31 + X28 + 1

0100 = 23-bit PN sequence—X23 + X18 + 1

0101 = 15-bit PN sequence—X15 + X14 + 1

0110 = 9-bit PN sequence—X9 + X5 + 1

0111 = 7-bit PN sequence—X7 + X6 + 1

1000 = ramp output

1110 = continuous/repeat user test

1111 = single user test

0x00

0x574

JESD204B

Link Mode

Control 4

ILAS delay

0000 = transmit ILAS on first LMFC after

SYNCINB± deasserted

0001 = transmit ILAS on second LMFC after

SYNCINB± deasserted

…

1111 = transmit ILAS on 16th LMFC after

SYNCINB± deasserted

Link layer test mode

000 = normal operation (link layer test

mode disabled)

001 = continuous sequence of /D21.5/

characters

100 = modified RPAT test sequence

101 = JSPAT test sequence

110 = JTSPAT test sequence

0x00

0x578

JESD204B

LMFC offset

LMFC phase offset value, Bits[4:0]

0x00

0x580

JESD204B DID

config

JESD204B Tx DID value, Bits[7:0]

0x00

0x581

JESD204B BID

config

JESD204B Tx BID value, Bits[7:0]

0x00

0x583

JESD204B LID

Config 1

Lane 0 LID value, Bits[4:0]

0x00

0x584

JESD204B LID

Config 2

Lane 1 LID value, Bits[4:0]

0x01

0x585

JESD204B LID

Config 3

Lane 2 LID value, Bits[4:0]

0x01

0x586

JESD204B LID

Config 4

Lane 3 LID value, Bits[4:0]

0x03

0x58B

JESD204B

parameters

SCR/L

JESD204B

scrambling

(SCR)

0 =

disabled

1 =

enabled

JESD204B lanes (L)

00 = 1 lane

01 = 2 lanes

11 = 4 lanes

Read only, see

0x8X

0x58C

JESD204B F

config

Number of octets per frame, F = Register 0x58C, Bits[7:0] + 1

0x88

Read only,

see

Reg. 0x570

0x58D

JESD204B K

config

Number of frames per multiframe, K = Register 0x58D, Bits[4:0] + 1

Only values where (F × K) mod 4 = 0 are supported

0x1F

See

Reg. 0x570

0x58E

JESD204B M

config

Number of converters per link, Bits[7:0]

0x00 = link connected to one virtual converter (M = 1)

0x01 = link connected to two virtual converters (M = 2)

0x03 = link connected to four virtual converters (M = 4)

0x07 = link connected to eight virtual converters (M = 8)

Read only

Rev. A | Page 62 of 66

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