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AD9484

Rev. A | Page 15 of 24

AD9484

AD8352

0Ω

0.1µF

VIN+

VIN– CML

0.1µF

8, 13

VCC

200Ω

ANALOG INPUT

Figure 30. Differential Input Configuration Using the AD8352

100Ω

0.1µF

240Ω

AD9510/AD9511/

AD9512/AD9513/

AD9514/AD9515

50Ω1

CLK

150Ω RESISTORS ARE OPTIONAL.

CLK–

CLK+

ADC

AD9484

PECL DRIVER

CLOCK

INPUT

CLOCK

INPUT

Figure 31. Differential PECL Sample Clock

100Ω

0.1µF

AD9510/AD9511/

AD9512/AD9513/

AD9514/AD9515

50Ω1

CLK

150Ω RESISTORS ARE OPTIONAL.

CLK–

CLK+

ADC

AD9484

LVDS DRIVER

CLOCK

INPUT

CLOCK

INPUT

Figure 32. Differential LVDS Sample Clock

CLOCK INPUT CONSIDERATIONS

For optimum performance, drive the AD9484 sample clock

inputs (CLK+ and CLK−) with a differential signal. This signal

is typically ac-coupled into the CLK+ and CLK− pins via a

transformer or capacitors. These pins are biased at ~0.9 V

internally and require no additional bias. If the clock signal is

dc-coupled, then the common-mode voltage should remain

within a range of 0.9 V.

Figure 33 shows one preferred method for clocking the AD9484.

The low jitter clock source is converted from single-ended to

differential using an RF transformer. The back-to-back Schottky

diodes across the secondary transformer limit clock excursions

into the AD9484 to approximately 0.8 V p-p differential. This

helps prevent the large voltage swings of the clock from feeding

through to other portions of the AD9484 and preserves the fast

rise and fall times of the signal, which are critical to low jitter

performance.

0.1µF

CLOCK

INPUT

50Ω

100Ω

CLK–

CLK+

ADC

AD9484

MINI-CIRCUITS

ADT1–1WT, 1:1Z

XFMR

SCHOTTKY

DIODES:

HSM2812

Figure 33. Transformer-Coupled Differential Clock

If a low jitter clock is available, another option is to ac couple a

differential PECL signal to the sample clock input pins, as

shown in Figure 31. The AD9510/AD9511/AD9512/AD9513/

AD9514/AD9515 family of clock drivers offers excellent jitter

performance.

In some applications, it may be acceptable to drive the sample

clock inputs with a single-ended 1.8 V CMOS signal. In such

applications, drive the CLK+ pin directly from a CMOS gate,

and bypass the CLK− pin to ground with a 0.1 μF capacitor in

parallel with a 39 kΩ resistor (see Figure 34).

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