80960JD datasheet(69/78 Pages) INTEL

69 / 78 page

Advance Information Datasheet

80960JA/JF/JD/JT 3.3 V Microprocessor

5.2

Boundary-Scan Register

The Boundary-Scan register contains a cell for each pin as well as cells for control of I/O and HIGHZ pins.

Table 25 shows the bit order of the 80960Jx processor Boundary-Scan register. All table cells that

contain “CTL” select the direction of bidirectional pins or HIGHZ output pins. If a “1” is loaded

into the control cell, the associated pin(s) are HIGHZ or selected as input.

Table 25.

Boundary-Scan Register Bit Order

Bit

Signal

Input/

Output

Bit

Signal

Input/

Output

Bit

Signal

Input/

Output

RDYRCV (TDI)

DEN

AD17

I/O

HOLD

HOLDA

AD16

I/O

2XINT0

ALE

AD15

I/O

3XINT1

I27

LOCK/ONCE

cell

Enable cell1

AD14

I/O

4XINT2

I28

LOCK/ONCE

I/O

AD13

I/O

5XINT3

BSTAT

AD12

I/O

6XINT4

I30

BE0

AD cells

Enable

cell1

7XINT5

I31

BE1

O55

AD11

I/O

8XINT6

I32

BE2

AD10

I/O

9XINT7

I33

BE3

O57

AD9

I/O

NMI

AD31

I/O

AD8

I/O

FAIL

AD30

I/O

AD7

I/O

ALE

AD29

I/O

AD6

I/O

WIDTH/HLTD1

AD28

I/O

AD5

I/O

WIDTH/HLTD0

AD27

I/O

AD4

I/O

AD26

I/O

AD3

I/O

AD25

I/O

AD2

I/O

CONTROL1

Enable cell1

AD24

I/O

AD1

I/O

CONTROL2

Enable cell1

AD23

I/O

AD0

I/O

BLAST

AD22

I/O

CLKIN

D/C

AD21

I/O

RESET

ADS

AD20

I/O

STEST

(TDO)

W/R

AD19

I/O

DT/R

AD18

I/O

NOTE:

1. Enable cells are active low.

80960JD Datasheet(PDF) 69 Page - Intel Corporation

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