AD5547/AD5557

Rev. 0 | Page 8 of 20

Table 5. Address Decoder Pins

A1

A0

Output Update

0

0

DAC A

0

1

None

1

0

DAC A and B

1

1

DAC B

Table 6. Control Inputs

RS

WR

LDAC

Register Operation

0

X

X

Reset the output to 0 with MSB pin = 0; reset the output to midscale with MSB pin = 1.

1

0

0

Load the input register with data bits.

1

1

1

Load the DAC register with the contents of the input register.

1

0

1

The input and DAC registers are transparent.

1

When LDAC and WR are tied together and programmed as a pulse, the data bits are loaded into the input register on

the falling edge of the pulse, and are then loaded into the DAC register on the rising edge of the pulse.

1

1

0

No register operation.