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GLT41016 Datasheet(PDF) 6 Page - List of Unclassifed Manufacturers

Part # GLT41016
Description  64K X 16 CMOS DYNAMIC RAM WITH EXTENDED DATA OUTPUT
PDF  23 Pages
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Manufacturer  ETC [List of Unclassifed Manufacturers]
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G -LINK
GLT41016
64K X 16 CMOS DYNAMIC RAM WITH EXTENDED DATA OUTPUT
Dec 1998 (Rev 2.1)
G-Link Technology Corporation
2701Northwestern Parkway
Santa Clara, CA 95051, U.S.A.
G-Link Technology Corporation, Taiwan
2F, No.12, R&D Rd. II, Science-Based Industrial Park,
Hsin Chu, Taiwan, R.O.C.
- 6 -
DC and Operating Characteristics (1-2)
TA = 0
°C to 70°C, V
CC=5V
±10%, V
SS=0V, unless otherwise specified.
Sym
.
Parameter
Test Conditions
Access
Time
Min.
Typ
Max.
Unit Notes
ILI
Input Leakage Current
(any input pin)
0V
≤ V
IN
≤ 5.5V
(All other pins not under
test=0V)
-10
+10
µA
ILO
Output Leakage Current
(for High-Z State)
0V
≤ V
out
≤ 5.5V
Output is disabled (Hiz)
-10
+10
µA
ICC1 Operating Current,
Random READ/WRITE
tRC = tRC (min.)
tRAC = 30ns
tRAC = 35ns
tRAC = 40ns
tRAC = 45ns
180
170
160
150
mA
1,2
ICC2 Standby Current,(TTL)
RAS , UCAS , LCAS at
VIH other inputs
≥V
SS
4
mA
ICC3 Refresh Current,
RAS -Only
RAS cycling, UCAS ,
LCAS at VIH
tRC = tRC (min.)
tRAC = 30ns
tRAC = 35ns
tRAC = 40ns
tRAC = 45ns
180
170
160
150
mA
2
ICC4 Operating Current,
EDO Page Mode
RAS at VIL,
UCAS , LCAS address
cycling: tPC = tPC(min.)
tRAC = 30ns
tRAC = 35ns
tRAC = 40ns
tRAC = 45ns
180
170
160
150
mA
1,2
ICC5 Refresh Current,
CAS Before RAS
RAS , UCAS , LCAS
address cycling:
tRC = tRC (min.)
tRAC = 30ns
tRAC = 35ns
tRAC = 40ns
tRAC = 45ns
180
170
160
150
mA
1
ICC6 Standby Current, (CMOS) RAS ≥V
CC-0.2V,
UCAS
≥V
CC-0.2V,
LCAS
≥V
CC-0.2V,
All other inputs VSS
2
mA
VIL
Input Low Voltage
-1
+0.8
V
3
VIH Input High Voltage
2.4
VCC+1
V
3
VOL Output Low Voltage
IOL = 4.2mA
0.4
V
VOH Output High Voltage
IOH = -5mA
2.4
V
Notes:
1. ICC is dependent on output loading when the device output is selected. Specified ICC(max.) is measured with the output
open.
2. ICC is dependent upon the number of address transitions specified ICC(max.) is measured with a maximum of one
transition per address cycle in random Read/Write and EDO Fast Page Mode.
3. Specified VIL(min.) is steady state operation. During transitions VIL(min.) may undershoot to -1.0V for a period not to
exceed 20ns. All AC parameters are measured with VIL(min.)
≥VSS and VIH(max.)≤VCC.



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