AD9289

Rev. 0 | Page 3 of 32

SPECIFICATIONS

AVDD = 3.0 V, DRVDD = 3.0 V, conversion rate = 65 MSPS, 2 V p-p differential input, 1.0 V internal reference, AIN = –0.5 dBFS, unless

otherwise noted.

Table 1.

Parameter

Temperature

Test Level

Min

Typ

Max

Unit

RESOLUTION

8

Bits

ACCURACY

No Missing Codes

Full

VI

Guaranteed

Offset Error

Full

VI

±5

±57

mV

Offset Matching

Full

VI

±12

±68

mV

Full

VI

±0.5

±2.5

% FS

Gain Matching1

Full

VI

±0.2

±0.9

% FS

Differential Nonlinearity (DNL)

25°C

V

±0.2

LSB

Full

VI

±0.2

±0.6

LSB

Integral Nonlinearity (INL)

25°C

V

±0.25

LSB

Full

VI

±0.25

±0.6

LSB

TEMPERATURE DRIFT

Offset Error

Full

V

±16

ppm/°C

Gain Error

1

Full

V

±40

ppm/°C

Reference Voltage (VREF = 1 V)

Full

V

±10

ppm/°C

REFERENCE

Output Voltage Error (VREF = 1 V)

Full

VI

±10

±35

mV

Load Regulation @ 1.0 mA (VREF = 1 V)

Full

V

0.7

mV

Output Voltage Error (VREF = 0.5 V)

Full

VI

±8

±26

mV

Load Regulation @ 0.5 mA (VREF = 0.5 V)

Full

V

0.2

mV

Input Resistance

Full

V

7

kΩ

COMMON MODE

Common-Mode Level Output

Full

VI

±1.5

±50

mV

ANALOG INPUTS

Differential Input Voltage Range (VREF = 1 V)

Full

VI

2

V p-p

Differential Input Voltage Range (VREF = 0.5 V)

Full

VI

1

V p-p

Common-Mode Voltage

Full

V

1.5

V

Input Capacitance

Full

V

5

pF

Analog Bandwidth, Full Power

Full

V

300

MHz

POWER SUPPLY

AVDD

Full

IV

2.7

3.0

3.3

V

DRVDD

Full

IV

2.7

3.0

3.3

V

IAVDD

2

Full

VI

150

168

mA

DRVDD

2

Full

VI

33

40

mA

Power Dissipation2

Full

VI

550

625

mW

Power-Down Dissipation

Full

VI

7

12

mW

CROSSTALK

Full

V

–75

dB