LT4351CMS datasheet(14/20 Pages) LINER

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LT4351

sn4351 4351fs

APPLICATIO S I FOR ATIO

Start-Up Considerations

There is no inherent shutdown in the part. As VIN ramps up,

the boost regulator starts at about 0.85V and becomes fully

operational by 1.1V. The undervoltage and overvoltage

comparators become accurate by 1.2V. The gate drive

amplifier keeps GATE low during this period with either a

passive pull-down, a weak active pull-down if OUT is greater

than 0.8V or with the full gate drive sink if VDD isabove2.2V.

Once VIN is greater than 1.2V and VDD is up, the part then

operates normally. The UV and OV pins will control the

enabling of the gate driver and once enabled, the VIN to

OUT voltage controls MOSFET turn on.

If VDD is still being charged when the gate driver turns on

the MOSFET, the GATE pin tracks with the VDD increase

until it reaches either the gate clamp voltage or the

compliance of the gate driver. If VDD is present without VIN

or OUT, the GATE pin actively sinks low.

Power Dissipation

The internal power dissipation of the LT4351 is comprised

of the following four major components: DC power dissi-

pation from VIN, DC power dissipation from VDD, the

dissipation in the boost switch including the base drive,

and dynamic power dissipation due to current used to

charge and discharge the MOSFETs. The DC components

are:

PDCVIN = IVIN • VIN

PDCVDD = IVDD • VDD

Figure 11 shows the internal dissipation of the boost

regulator as a function of VIN and inductor value. Figure 11

represents the worst-case condition with the regulator on

all the time, which does not occur in normal practice.

Since the boost regulator supplies current for VDD, the

current is the VDD supply current (3.5mA) plus the average

current to charge the gate. For a gate charge of 50nC at a

10kHz rate, this adds 0.5mA of current. The power dissi-

pated by the boost regulator to supply the 4mA is shown

in Figure 12, representing a more typical situation.

Finally, the gate driver dissipates power internally when

charging and discharging the gate of the MOSFETs. This

power depends on the input capacitance of the MOSFETs

and the frequency of charge and discharge. The power

associated with this can be approximated by:

GATE









••

•

–

where QG is the required gate charge to charge the

MOSFET to the clamp voltage (7.4V) and fG is the fre-

quency at which the gate is charged and discharged.

Normally fG is low and the resulting power would be very

low. Figure 13 shows PGATE for a 50nC gate charge at a

1kHz rate.

Total power dissipation is the sum of all of PDCVIN, PDCVDD,

PBOOST and PGATE. Figure 14 is representative of the total

power dissipation of a typical application at steady state.

Figure 11. PBOOST(MAX)

Figure 12. PBOOST(TYP)

VIN (V)

0.20

0.25

L = 10

µH

L = 4.7

µH

4351 F11

0.15

0.10

0.30

VIN (V)

0.015

0.020

L = 4.7

µH

4351 F12

0.010

0.005

0.025

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