VSP5000

SLES057 – DECEMBER 2002

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9

VSP5000 SH Mode Timing Specification (Even and Odd Channels)

CCD

Output

Signal

(Even/

Odd)

SYSCLK

B[11:0]

N+1

N

N+2

tw(D)

td(S)

t(CKP)

t(CKP)

t(ADC)

t(ADC)

td(O)

th(O)

N

*10

(EV)

SHD

N+3

N

*10

(OD)

N

*9

(EV)

N

*9

(OD)

N

*8

(EV)

N

*8

(OD)

N

*7

(EV)

t(DS)

SYMBOL

PARAMETER

MIN

TYP

MAX

UNIT

t(CKP)

Clock period

33

ns

t(ADC)

SYSCLK pulse width

16.7

ns

tw(D)

SHD pulse width

6

8.3

ns

td(S)

Sampling delay

3.5

ns

t(DS)

SHD trailing edge to SYSCLK leading edge

–8

6

ns

th(O)

Output hold time(1)

6

ns

t

Output delay at data output delay = 0 ns(1)

9

ns

td(O)

Output delay at data output delay = 3 ns(2)

13

ns

DL

Data latency

9

Clock

Cycles

(1) Load = 25 pF, data output delay = 0 ns, meaning the delay time setting by configuration register of the serial interface.

(2) Load = 25 pF, data output delay = 3 ns, meaning the delay time setting by configuration register of the serial interface.