SMH4811AS datasheet(3/16 Pages) SUMMIT

3 / 16 page

2044 6.1 2/8/01

SMH4811A

SUMMIT MICROELECTRONICS, Inc.

Preliminary

PIN DESCRIPTIONS

DRAIN SENSE (1)

The DRAIN SENSE input monitors the voltage at the drain

of the external power MOSFET switch with respect to VSS.

An internal 10µA source pulls the DRAIN SENSE signal

towards the 5V reference level. DRAIN SENSE must be

held below 2.5V to enable the PG outputs.

VGATE (2)

The VGATE output activates an external power MOSFET

switch. This signal supplies a constant current output

(100µA typical), which allows easy adjustment of the

MOSFET turn on slew rate.

EN/TS (3)

The Enable/Temperature Sense input is the master en-

able input. If EN/TS is less than 2.5V, VGATE will be

disabled. This pin has an internal 200k

Ω pull-up to 5V.

PD1# and PD2# (4 & 5)

These are logic level active low inputs that can optionally

be employed to enable VGATE and the PG outputs when

they are at VSS. These pins each have an internal 50k

Ω

pull-up to 5V.

FAULT# (6)

This is an open-drain, active-low output that indicates the

fault status of the device.

CBSENSE (7)

The circuit breaker sense input is used to detect over-

current conditions across an external, low value sense

resistor (RS) tied in series with the Power MOSFET. A

voltage drop of greater than 50mV across the resistor for

longer than tCBD will trip the circuit breaker. A program-

mable Quick-Trip™ sense point is also available.

UV (9)

The UV pin is used as an under-voltage supply monitor,

typically in conjunction with an external resistor ladder.

VGATE will be disabled if UV is less than 2.5V. Program-

mable internal hysteresis is available on the UV input,

adjustable in increments of 62.5mV. Also available is a

filter delay on the UV input.

OV (10)

The OV pin is used as an over-voltage supply monitor,

typically in conjunction with an external resistor ladder.

VGATE will be disabled if OV is greater than 2.5V. A filter

delay is available on the OV input.

5.0VREF & 2.5VREF (11 & 12)

These are precision 5V and 2.5V output reference volt-

ages that may be use to expand the logic input functions

on the SMH4803A. The reference outputs are with re-

spect to VSS.

ENPG (14)

This is an active high input that controls the PG# output.

When ENPG is pulled low the PG# output is immediately

placed in a high impedance state. This pin has an internal

50k

Ω pull-up to 5V.

PG# (15)

The PG# pin is an open-drain, active-low output with no

internal pull-up resistor. It can be used to switch a load or

enable a DC/DC converter. PG# is enabled immediately

after VGATE reaches VDD – VGT and the DRAIN SENSE

voltage is less than 2.5V. Voltage on these pins cannot

exceed 12V, as referenced to VSS.

VDD (16)

VDD is the positive supply connection. An internal shunt

regulator limits the voltage on this pin to approximately

12V with respect to VSS. A resistor must be placed in

series with the VDD pin to limit the regulator current (RD in

the application illustrations).

VSS (8)

VSS is connected to the negative side of the supply.

SMH4811AS Datasheet(PDF) 3 Page - Summit Microelectronics, Inc.

SMH4811AS Datasheet(HTML) 3 Page - Summit Microelectronics, Inc.

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

Datasheet Download

Link URL