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TUSB564 Datasheet(PDF) 25 Page - Texas Instruments

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Part # TUSB564
Description  USB TYPE-C DP Alt Mode 8.1 Gbps Sink-Side Linear Redriver Crosspoint Switch
PDF  45 Pages
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Manufacturer  TI1 [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI1 - Texas Instruments

TUSB564 Datasheet(HTML) 25 Page - Texas Instruments

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TUSB564
www.ti.com
SLLSF29A – OCTOBER 2017 – REVISED OCTOBER 2017
Product Folder Links: TUSB564
Submit Documentation Feedback
Copyright © 2017, Texas Instruments Incorporated
8.6 Register Maps
8.6.1 General Register (address = 0x0A) [reset = 00000001]
Figure 18. General Registers
7
6
5
4
3
2
1
0
Reserved
SWAP_HPDIN
EQ_OVERRID
E
HPDIN_OVRRI
DE
FLIPSEL
CTLSEL[1:0].
R
R/W
R/W
R/W
R/W
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 11. General Registers
Bit
Field
Type
Reset
Description
7:5
Reserved.
R
00
Reserved.
4
EQ_OVERRIDE
R/W
0
Setting of this field will allow software to use EQ settings from
registers instead of value sample from pins.
0 – EQ settings based on sampled state of the EQ pins
(SSEQ[1:0], EQ[1:0], and DPEQ[1:0]).
1 – EQ settings based on programmed value of each of the EQ
registers
3
DP_EN_CTRL
R/W
0
Controls whether DisplayPort functionality is controlled by
CTLSEL1 register or CTL1 pin.
0 – DisplayPort enable/disable is based on CTLSEL1 register.
1 – DisplayPort enable/disable is based on state of CTL1 pin.
2
FLIPSEL
R/W
0
FLIPSEL. Refer to Table 5 and Table 6 for this field functionality.
1:0
CTLSEL[1:0].
R/W
01
00 – Disabled. All RX and TX for USB3 and DisplayPort are
disabled.
01 – USB3.1 only enabled. (Default)
10 – Four DisplayPort lanes enabled.
11 – Two DisplayPort lanes and one USB3.1
8.6.2 DisplayPort Control/Status Registers (address = 0x10) [reset = 00000000]
Figure 19. DisplayPort Control/Status Registers (0x10)
7
6
5
4
3
2
1
0
DP1EQ_SEL
DP0EQ_SEL
R/W/U
R/W/U
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 12. DisplayPort Control/Status Registers (0x10)
Bit
Field
Type
Reset
Description
7:4
DP1EQ_SEL
R/W/U
0000
Field selects EQ level for DP lane 1. When EQ_OVERRIDE =
1’b0, this field reflects the sampled state of DPEQ[1:0] pins.
When EQ_OVERRIDE = 1’b1, software can change the EQ
setting for DP lane 1 based on value written to this field.
3:0
DP3EQ_SEL
R/W/U
0000
Field selects EQ level for DP lane 3. When EQ_OVERRIDE =
1’b0, this field reflects the sampled state of DPEQ[1:0] pins.
When EQ_OVERRIDE = 1’b1, software can change the EQ
setting for DP lane 3 based on value written to this field.



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