SPT

7

11/12/98

SPT9110

Figure 3 - Typical Interface Circuit (Single-Ended Operational Design)

N/C

N/C

5

6

7

8

A+5V

1

2

3

4

Q0

GND

DO

VCC

D1

Q1

GND(Ref)

REF OUT

REF IN

GND(THA)

GND(SUB)

GND(CAP)

Analog IN

GND(THA)

GND(THA)

GND(THA)

GND(THA)

AVCC(Ref)

GND(SUB)

GND(INV)

CLK

AVCC(THA)

OUT+

OUT-

INV A

INV B

AVCC(INV)

AVCC(ESD)

AVCC(THA)

AVCC(THA)

AVCC(THA)

AVCC(THA)

AVCC(INV)

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

10

300

50

50

1 µF

0.01 µF

A+5V

0.1 µF

TTL Clock

(Sample Clock, up to 100 MHz)

(+3.0 V)

A+5V

A+5V

OUT

4.7 µF

0.01 µF

0.01 µF

A+5V

0.01 µF

4.7 µF

0.1 µF

(+2.5 V)

XUF (Dependent on Frequency)

50

-

+

OP191

2

3

7

4

6

0.01 µF

(Optional Level-Shift Circuit)

+

+

+

4.7 µF

22

(TTL to PECL

Translator)

22

Analog In

CLK

Q0

Q1

Notes:

1. Input signal is typically at a +2.5 V offset. The optional level-shift circuit may be eliminated if

driving from a source that already provides for this offset.

2. The device may be operated from -5 V supply on GND pins and 0 V on AVCC pins. All input and

output pins will be shifted by -5 V. The use of an ECL level may be used to drive the clock inputs.

3. VCC (ESD) is the high voltage for the ESD protection diodes and must be connected in all

applications. NOTE: It should be tied to VCC (THA), not to VCC (INV).

N/C

N/C

N/C

N/C

0.01 µF

Figure 4 - Typical Interface Circuit (Differential Operational Design)

5

6

7

8

A+5V

1

2

3

4

Q0

GND

DO

VCC

D1

Q1

GND(Ref)

REF OUT

REF IN

GND(THA)

GND(SUB)

GND(CAP)

Analog IN

GND(THA)

GND(THA)

GND(THA)

GND(THA)

AVCC(Ref)

GND(SUB)

GND(INV)

CLK

AVCC(THA)

OUT+

OUT-

INV A

INV B

AVCC(INV)

AVCC(ESD)

AVCC(THA)

AVCC(THA)

AVCC(THA)

AVCC(THA)

AVCC(INV)

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

10

300

50

50

1 µF

0.01 µF

A+5V

0.1 µF

TTL Clock

(Sample Clock, up to 100 MHz)

(+3.0 V)

A+5V

A+5V

OUT+

OUT-

4.7 µF

0.01 µF

4.7 µF

0.01 µF

A+5V

0.01 µF

4.7 µF

4.7 µF

0.01 µF

0.1 µF

(+2.5 V)

XUF (Dependent on Frequency)

50

-

+

OP191

2

3

7

4

6

0.01 µF

(Optional Level-Shift Circuit)

(Differential Output)

+

+

+

+

+

22

(TTL to PECL

Translator)

22

22

Analog In

CLK

Q0

Q1

Notes:

1. Input signal is typically at a +2.5 V offset. The optional level-shift circuit may be eliminated if

driving from a source that already provides for this offset.

2. The device may be operated from -5 V supply on GND pins and 0 V on AVCC pins. All input and

output pins will be shifted by -5 V. The use of an ECL level may be used to drive the clock inputs.

3. VCC (ESD) is the high voltage for the ESD protection diodes and must be connected in all

applications. NOTE: It should be tied to VCC (THA), not to VCC (INV).