ST92F120JR9Q6 datasheet(41/324 Pages) STMICROELECTRONICS

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ST92F120 - SINGLE VOLTAGE FLASH & EEPROM

FUNCTIONAL DESCRIPTION (Cont’d)

3.2.3 Operation

The memory has a register interface mapped in

memory space (segment 22h). All operations are

enabled through the FCR (Flash Control Register)

ECR (EEPROM Control Register).

All operations on the Flash must be executed from

another memory (internal RAM, EEPROM, exter-

nal memory).

Flash (including TestFlash) and EEPROM have

duplicated sense amplifiers, so that one can be

read while the other is written. However simultane-

ous Flash and EEPROM write operations are for-

bidden.

An interrupt can be generated at the end of a

Flash or an EEPROM write operation: this inter-

rupt is multiplexed with an external interrupt EX-

TINTx (device dependent) to generate an interrupt

INTx.

The status of a write operation inside the Flash

and the EEPROM memories can be monitored

through the FESR[1:0] registers.

Control and Status registers are mapped in mem-

ory (segment 22h), as shown in the following fig-

ure.

Figure 22. Control and Status Register Map

During a write operation, if the power supply drops

or the RESET pin is activated, the write operation

is immediately interrupted. In this case the user

must repeat the last write operation following pow-

er on or reset.

224000h

224001h

224002h

FCR

ECR

FESR0

FESR1

224003h

ST92F120JR9Q6 Datasheet(PDF) 41 Page - STMicroelectronics