AD7143 datasheet(39/57 Pages) AD

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AD7143

Rev. 0 | Page 38 of 56

Table 21. STAGE_LOW_INT_EN Register

Address

Data Bit

Default

Type

Name

Description

[0]

STAGE0_LOW_INT_EN

STAGE0 low interrupt enable

0 = interrupt source disabled

1 = INT asserted if STAGE0 low threshold is exceeded

[1]

STAGE1_LOW_INT_EN

STAGE1 low interrupt enable

0 = interrupt source disabled

1 = INT asserted if STAGE0 low threshold is exceeded

[2]

STAGE2_LOW_INT_EN

STAGE2 low interrupt enable

0 = interrupt source disabled

1 = INT asserted if STAGE0 low threshold is exceeded

[3]

STAGE3_LOW_INT_EN

STAGE3 low interrupt enable

0 = interrupt source disabled

1 = INT asserted if STAGE0 low threshold is exceeded

[4]

STAGE4_LOW_INT_EN

STAGE4 low interrupt enable

0 = interrupt source disabled

1 = INT asserted if STAGE0 low threshold is exceeded

0x005

[5]

STAGE5_LOW_INT_EN

STAGE5 low interrupt enable

0 = interrupt source disabled

1 = INT asserted if STAGE0 low threshold is exceeded

R/W

[6]

STAGE6_LOW_INT_EN

STAGE6 low interrupt enable

0 = interrupt source disabled

1 = INT asserted if STAGE0 low threshold is exceeded

[7]

STAGE7_LOW_INT_EN

STAGE7 low interrupt enable

0 = interrupt source disabled

1 = INT asserted if STAGE0 low threshold is exceeded

[11:8]

Unused

Set unused register bits = 0

[15:12]

TESTMODE

Set test mode register bits = 0 (at all times)

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