AD7873ACPZ datasheet(6/29 Pages) AD

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Data Sheet

AD7873

Rev. F | Page 5 of 28

TIMING SPECIFICATIONS

TA = TMIN to TMAX, unless otherwise noted; VCC = 2.7 V to 5.25 V, VREF = 2.5 V.

Table 2. Timing Specifications1

Parameter

Limit at TMIN, TMAX

Unit

Description

fDCLK2

kHz min

MHz max

tACQ

1.5

µs min

Acquisition time

ns min

CS falling edge to first DCLK rising edge

ns max

CS falling edge to busy three-state disabled

t33

ns max

CS falling edge to DOUT three-state disabled

200

ns min

DCLK high pulse width

200

ns min

DCLK low pulse width

ns max

DCLK falling edge to BUSY rising edge

ns min

Data setup time prior to DCLK rising edge

ns min

Data valid to DCLK hold time

t93

200

ns max

Data access time after DCLK falling edge

t10

ns min

CS rising edge to DCLK ignored

t11

100

ns max

CS rising edge to BUSY high impedance

t124

100

ns max

CS rising edge to DOUT high impedance

Sample tested at 25°C to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of VCC) and timed from a voltage level of 1.6 V.

Mark/space ratio for the DCLK input is 40/60 to 60/40.

Measured with the load circuit of Figure 2 and defined as the time required for the output to cross 0.4 V or 2.0 V.

t12 is derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 2. The measured number is then extrapolated

back to remove the effects of charging or discharging the 50 pF capacitor. This means that the time, t12, quoted in the timing characteristics is the true bus relinquish

time of the part and is independent of the bus loading.

Figure 2. Load Circuit for Digital Output Timing Specifications

200µA

IOL

200µA

IOH

1.6V

TO OUTPUT

50pF

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