SWITCHING SPECIFICATIONS AT T

0

I

F

V

O

1.3V

1.3V

5V

t

PHL

t

PLH

V

OL

DB91038-AAS/A3

7/12/00

2

I

100

Ω

R

L

V

O

C

8

7

6

5

I

F

1

4

3

10% Duty Cycle

1/f < 100

µs

5V

PARAMETER

SYM DEVICE

MIN TYP MAX UNITS

TEST CONDITION

0.8

1.5

µs

I

Propagation Delay Time

t

PHL

(note 10 )

to Logic Low at Output ( fig 1 )

0.3

1.5

µs

I

(note11 )

1.0

2.5

µs

I

Propagation Delay Time

t

PLH

(note 10 )

to Logic High at Output ( fig 1 )

1.1

2.5

µs

I

(note11 )

1000

V/

µs

I

Common Mode Transient

R

Immunity at Logic High

CM

H

Level Output ( fig 2 )

1000

V/

µs

I

R

-1000

V/

µs

I

Common Mode Transient

R

Immunity at Logic Low

CM

L

Level Output ( fig 2 )

-1000

V/

µs

I

R

NOTES:-

1.

2.

3.

4.

5.

Each channel .

6.

CURRENT TRANSFER RATIO is defined as the ratio of output collector current,I

input current, I

7.

Device considered a two-terminal device: pins 1,2,3,and 4 shorted together and pins 5,6,7,and 8 shorted

together.

8.

Measured between pins 1 and 2 shorted together, and pins 3 and 4 shorted together.

9.

Common mode transient immunity in Logic High level is the maximum tolerable (positive) dVcm/dt on

the leading edge of the common mode pulse V

state (i.e. V

Common mode transient immunity in Logic Low level is the maximum tolerable

(negative) dVcm/dt on the trailing edge of the common mode pulse signal, V

will remain in Logic Low state (i.e. V

10. The 7.5k

Ω load represents 1 LSTTL unit load of 0.36mA and a 20kΩ pull-up resistor.

11. The 4.7k

Ω load represents 1 LSTTL unit load of 0.36mA and a 8.2kΩ pull-up resistor.

12. The 2500 V

FIG.1 SWITCHING TEST CIRCUIT

PULSE

GENERATOR

Z

t