LC823450 datasheet(61/112 Pages) ONSEMI

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LC823450

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PLL Characteristics

PLL1 (System)

Table 21. PLL1 (SYSTEM) (VDD1 (Note 31) = 0.93 to 1.27 V, TA = −20°C to +65°C)

Item

Symbol

condition

AVDDPLL1 = 0.93 to 1.1 V

AVDDPLL1 = 1.1 to 1.3 V

Unit

Min

Typ

Max

Min

Typ

Max

VCO Voltage

VCNT1

AVDD

PLL1

same as left

The VCO

Highest Oscillation

Frequency

Fmax

200

360

MHz

The VCO

Lowest Oscillation

Frequency

Fmin

180

MHz

Phase Comparison

Frequency

Fref

same as left

MHz

PLL Lock Time

Tlock1

(Note 33)

Fref >=

32.768

KHz

same as left

Tlock2

(Note 33)

Fref >= 1

MHz

3.5

same as left

Jitter (Note 32)

Jitter

±3.19

±5.42

±4.28

±7.28

31. Power up and power down timing of AVDDPLL1 and Vdd1 should be as close as possible.

32. Result of simulation

33. PLL lock time and appropriate LPF circuit depend on Phase comparison frequency (Fref).

Refer to 5−2 PLL1(System) for appropriate LPF circuit

PLL2 (Audio)

Table 22. PLL2 (AUDIO) (VDD1 (Note 34) = 0.93 to 1.27 V, TA = −20°C to +65°C)

Item

Symbol

Condition

AVDDPLL1 = 0.93 to 1.1 V

Unit

Min

Typ

Max

VCO voltage

VCNT2

AVDDPLL2

The VCO

Highest Oscillation Frequency

Fmax

150

MHz

The VCO

Lowest Oscillation Frequency

Fmin

MHz

Phase Comparison

Frequency

Fref

MHz

PLL Lock Time

Tlock1 (Note

36)

Fref >=

6.4 KHz

Tlock2 (Note

36)

Fref >=

38.4 KHz

Jitter (Note 35)

Jitter

±3.28

±5.58

34. Power up and power down timing of AVDDPLL2 and Vdd1 should be as close as possible

35. Result of simulation

36. Phase comparison frequency(Fref) depends on frequency of xtal oscillation as described in the table below.

PLL lock time and appropriate LPF circuit depend on Fref.

− Tlock1 is derived from the case when XT1 is one of 12, 20, 24, 48 MHz.

− Tlock2 is derived from the case when XT1 is 24 MHz.

Refer to 5 − 3 PLL2(Audio) for appropriate LPF circuit

LC823450 Datasheet(PDF) 61 Page - ON Semiconductor

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