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AD2S1200YST Datasheet(PDF) 14 Page - Analog Devices |
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AD2S1200YST Datasheet(HTML) 14 Page - Analog Devices |
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14 / 25 page ![]() AD2S1200 Rev. 0 | Page 13 of 24 t3 t6 t7 tCK CLKIN DATA DON'T CARE VEL POS t2 SAMPLE CS RD RDVEL t1 t1 t3 t5 t4 t5 t4 t7 t6 Figure 7. Parallel Port Read Timing Table 5. Parallel Port Timing Parameter Description Min Typ Max tCK Clock Period (= 1/8.192 MHz) ~122 ns t1 SAMPLE Pulse Width 2 × tCK + 20 ns t2 Delay from SAMPLE before RD/CS Low 6 × tCK + 20 ns t3 RD Pulse Width 18 ns t4 Set Time RDVEL before RD/CS Low 5 ns t5 Hold Time RDVEL after RD/CS Low 7 ns t6 Enable Delay RD/CS Low to Data Valid 12 ns t7 Disable Delay RD/CS Low to Data High Z 18 ns |
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