AD2S1210WDSTZ datasheet(23/37 Pages) AD

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AD2S1210

Rev. A | Page 22 of 36

DOS RESET MAXIMUM AND MINIMUM

THRESHOLD REGISTERS

Table 16. 8-Bit Registers

Address

Bit

Read/Write

0x8B

D7 to D0

Read/write

0x8C

D7 to D0

Read/write

The AD2S1210 continuously stores the minimum and maximum

magnitude of the monitor signal in internal registers. The differ-

ence between the minimum and maximum is calculated to

determine if a DOS mismatch has occurred. The initial values

for the minimum and maximum internal registers must be

defined by the user. When the fault register is cleared, the

registers that store the maximum and minimum amplitudes of

the monitor signal are reset to the values stored in the DOS reset

maximum and minimum threshold registers. The resolution of

the DOS reset maximum and minimum thresholds is seven bits

each, that is, 38 mV. Note that the MSB, D7, should be set to

0.To ensure correct operation, it is recommended that the DOS

reset minimum threshold register be set to at least 1 LSB less

than the DOS overrange threshold, and the DOS reset maximum

threshold register be set to at least 1 LSB greater than the LOS

threshold register. The default value of the DOS reset minimum

threshold register and the DOS reset maximum threshold

LOT HIGH THRESHOLD REGISTER

Table 17. 8-Bit Register

Address

Bit

Read/Write

0x8D

D7 to D0

Read/write

The LOT high threshold register determines the loss of position

tracking threshold for the AD2S1210. The LOT high threshold

is a 7-bit word. Note that the MSB, D7, should be set to 0. The

range of the LOT high threshold, the LSB size, and the default

value of the LOT high threshold on power-up are dependent on

the resolution setting of the AD2S1210, and are outlined in

Table 19.

LOT LOW THRESHOLD REGISTER

Table 18. 8-Bit Register

Address

Bit

Read/Write

0x8E

D7 to D0

Read/write

The LOT low threshold register determines the level of hysteresis

on the loss of position tracking fault detection. Loss of tracking

(LOT) occurs when the internal error signal of the AD2S1210

exceeds the LOT high threshold. LOT has hysteresis and is not

cleared until the internal error signal is less than the value defined

in the LOT low threshold register. The LOT low threshold is a

7-bit word. Note that the MSB, D7, should be set to 0. The range

of the LOT high threshold, the LSB size, and the default value of

the LOT high threshold on power-up are dependent on the resolu-

tion setting of the AD2S1210, and are outlined in Table 19.

Table 19. LOT High/Low Threshold

Resolution

(Bits)

Range

(Degrees)

LSB Size

(Degrees)

LOT Low

Default

(Degrees)

LOT High

Default

(Degrees)

0 to 45

0.35

2.5

12.5

0 to 18

0.14

1.0

5.0

0 to 9

0.09

0.5

2.5

0 to 9

0.09

0.5

2.5

EXCITATION FREQUENCY REGISTER

Table 20. 8-Bit Register

Address

Bit

Read/Write

0x91

D7 to D0

Read/write

The excitation frequency register determines the frequency of

the excitation outputs of the AD2S1210. A 7-bit frequency control

word is written to the register to set the excitation frequency.

Note that the MSB, D7, should be set to 0.

(

)

CLKIN

Frequency

Excitation

FCW

(9)

where FCW is the frequency control word and fCLKIN is the clock

frequency of the AD2S1210. The specified range of the excitation

frequency is from 2 kHz to 20 kHz and can be set in increments

of 250 Hz. To ensure that the AD2S1210 is operated within the

specified frequency range, the frequency control word should

be a value between 0x4 and 0x50.

For example, if the user requires an excitation frequency of 5 kHz

and has an 8.192 MHz clock frequency, the code that needs to

be programmed is given by

(

)

MHz

192

kHz

FCW

(hexadecimal)

The default excitation frequency of the AD2S1210 on power-up

is 10 kHz.

CONTROL REGISTER

Table 21. 8-Bit Register

Address

Bit

Read/Write

0x92

D7 to D0

Read/write

The control register is an 8-bit register that sets the AD2S1210

control modes. The default value of the control register on

power-up is 0x7E.

Table 22. Control Register Bit Descriptions

Bit

Description

Address/data bit

Reserved; set to 1

Phase lock range

0 = 360°, 1 = ±44°

0 = disable hysteresis, 1 = enable hysteresis

Set Encoder Resolution EnRES1

Set Encoder Resolution EnRES0

Set Resolution RES1

Set Resolution RES0

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