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AD7195

Data Sheet

Rev. A | Page 38 of 44

Simultaneous 50 Hz and 60 Hz rejection is obtained when

FS[9:0] is set to 480 (master clock = 4.92 MHz), as shown in

Figure 38. The output data rate is 10 Hz when zero latency is

disabled and 3.3 Hz when zero latency is enabled. The sinc3

filter has rejection of 100 dB minimum at 50 Hz ± 1 Hz and

60 Hz ± 1 Hz.

–120

–110

–100

–90

–80

–70

–60

–50

–40

–30

–20

–10

120

150

FREQUENCY (Hz)

Figure 38. Sinc3 Filter Response (FS[9:0] = 480)

Simultaneous 50 Hz/60 Hz rejection is also achieved using the

REJ60 bit in the mode register. When FS[9:0] is programmed to

96 and the REJ60 bit is set to 1, notches are placed at both 50 Hz

and 60 Hz for a stable 4.92 MHz master clock. Figure 39 shows

the frequency response of the sinc3 filter with this configuration.

Assuming a stable clock, the rejection at 50 Hz/60 Hz (±1 Hz)

is in excess of 67 dB minimum.

–120

–110

–100

–90

–80

–70

–60

–50

–40

–30

–20

–10

100

125

150

FREQUENCY (Hz)

Figure 39. Sinc3 Filter Response (FS[9:0] = 96, REJ60 = 1)

CHOP ENABLED (SINC4 FILTER)

With chop enabled, the ADC offset and offset drift are minimized.

The analog input pins are continuously swapped. With the

analog input pins connected in one direction, the settling time

of the sinc filter is allowed and a conversion is recorded. The

analog input pins are then inverted, and another settled conver-

sion is obtained. Subsequent conversions are averaged to

minimize the offset. This continuous swapping of the analog

input pins and the averaging of subsequent conversions means

that the offset drift is also minimized. With chop enabled, the

resolution increases by 0.5 bits.

SINC3/SINC4

MODULATOR

ADC

CHOP

Figure 40. Chop Enabled

Output Data Rate and Settling Time (Sinc4 Chop

Enabled)

For the sinc4 filter, the output data rate is equal to

fADC = fCLK/(4 × 1024 × FS[9:0])

where:

fADC is the output data rate.

fCLK is the master clock (4.92 MHz nominal).

FS[9:0] is the decimal equivalent of Bit FS9 to Bit FS0 in the

mode register.

The value of FS[9:0] can be varied from 1 to 1023. This results

in an output data rate of 1.17 Hz to 1200 Hz. The settling time is

equal to

tSETTLE = 2/fADC

Table 33 gives some examples of FS[9:0] values and the corres-

ponding output data rates and settling times.

Table 33. Examples of Output Data Rates and the

Corresponding Settling Time

FS[9:0]

Output Data Rate (Hz)

Settling Time (ms)

12.5

160

133

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