AD7357BCPZ datasheet(19/25 Pages) AD

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AD7357

Data Sheet

Rev. E | Page 18 of 24

MODES OF OPERATION

The AD7357 mode of operation is selected by controlling the

logic state of the CS signal during a conversion. There are three

possible modes of operation: normal mode, partial power-down

mode, and full power-down mode. After a conversion is initiated,

the point at which CS is pulled high determines which power-

down mode, if any, the device enters. Similarly, if already in a

power-down mode, CS can control whether the device returns

to normal operation or remains in a power-down mode. These

modes of operation are designed to provide flexible power

management options. These options can be chosen to optimize

the power dissipation and throughput rate ratio for the differing

application requirements.

NORMAL MODE

Normal mode is intended for applications needing the fastest

throughput rates. The user does not need to worry about any

power-up times because the AD7357 remains fully powered at

all times. Figure 25 shows the general diagram of the operation

of the AD7357 in this mode.

SCLK

LEADING ZEROS + CONVERSION RESULT

114

SDATAA

SDATAB

Figure 25. Normal Mode Operation

The conversion is initiated on the falling edge of CS, as described

in the Serial Interface section. To ensure that the device remains

fully powered up at all times, CS must remain low until at least

10 SCLK falling edges have elapsed after the falling edge of CS.

If CS is brought high any time after the 10th SCLK falling edge

but before the 16th SCLK falling edge, the device remains powered

up, but the conversion is terminated and SDATAA and SDATAB

go back into three-state. To complete the conversion and access

the conversion result for the AD7357, 16 serial clock cycles are

required. SDATA lines do not return to three-state after 16 SCLK

cycles have elapsed, but instead do so when CS is brought high

again. If CS is left low for another 2 SCLK cycles, two trailing

zeros are clocked out after the data. If CS is left low for a further

16 SCLK cycles, the result for the other ADC on board is also

accessed on the same SDATA line as shown in Figure 32 (see

the Serial Interface section).

When 32 SCLK cycles have elapsed, the SDATA line returns to

three-state on the 32nd SCLK falling edge. If CS is brought high

prior to this, the SDATA line returns to three-state at that point.

Thus, CS may idle low after 32 SCLK cycles until it is brought

high again sometime prior to the next conversion, if so desired,

because the bus still returns to three-state upon completion of

the dual result read.

When a data transfer is complete and SDATAA and SDATAB have

returned to three-state, another conversion can be initiated after

the quiet time, tQUIET, has elapsed by bringing CS low again

(assuming the required acquisition time has been allowed).

PARTIAL POWER-DOWN MODE

This mode is intended for use in applications where slower

throughput rates are required. Either the ADC is powered down

between each conversion or a series of conversions can be

performed at a high throughput rate and the ADC is then

powered down for a relatively long duration between these

bursts of several conversions. When the AD7357 is in partial

power-down mode, all analog circuitry is powered down except

for the on-chip reference and reference buffers.

To enter partial power-down mode, interrupt the conversion

process by bringing CS high anywhere after the second falling

edge of SCLK and before the 10th falling edge of SCLK, as shown in

Figure 26. When CS is brought high in this window of SCLKs,

the device enters partial power-down mode, the conversion that

was initiated by the falling edge of CS is terminated, and SDATAA

and SDATAB go back into three-state. If CS is brought high before

the second SCLK falling edge, the device remains in normal mode

and does not power down. This avoids accidental power-down

due to glitches on the CS line.

SCLK

THREE-STATE

SDATAA

SDATAB

114

Figure 26. Entering Partial Power-Down Mode

To exit this mode of operation and to power up the AD7357 again,

perform a dummy conversion. On the falling edge of CS, the device

begins to power up and continues to power up as long as CS is

held low until after the falling edge of the 10th SCLK. The device

is fully powered up after approximately 200 ns elapses (or one

full conversion), and valid data results from the next conversion, as

shown in Figure 27. If CS is brought high before the second falling

edge of SCLK, the AD7357 again goes into partial power-down

mode. This avoids accidental power-up due to glitches on the

CS line. Although the device may begin to power up on the falling

edge of CS, it powers down again on the rising edge of CS. If the

AD7357 is already in partial power-down mode and CS is brought

high between the second and 10th falling edges of SCLK, the device

enters full power-down mode.

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