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AD7357

Data Sheet

Rev. E | Page 20 of 24

POWER-UP TIMES

The AD7357 has two power-down modes: partial power-down

and full power-down. They are described in detail in the Partial

Power-Down Mode section and the Full Power-Down Mode

section. This section describes the power-up time required when

coming out of either of these modes. Note that the power-up

times apply with the recommended decoupling capacitors in place

on the REFA and REFB pins.

To power up from partial power-down mode, one dummy cycle

is required. The device is fully powered up after approximately

200 ns from the falling edge of CS has elapsed. As soon as the

partial power-up time has elapsed, the ADC is fully powered up

and the input signal is acquired properly. The quiet time, tQUIET,

must still be allowed from the point where the bus goes back into

three-state after the dummy conversion to the next falling

edge of CS.

To power up from full power-down, allow approximately 6 ms

from the falling edge of CS, shown in Figure 29 as tPOWER-UP2.

Note that during power-up from partial power-down mode, the

track-and-hold, which is in hold mode while the device is powered

down, returns to track mode after the first SCLK edge that the

device receives after the falling edge of CS.

When power supplies are first applied to the AD7357, the ADC

powers up in either of the power-down modes or in normal mode.

Because of this, it is best to allow a dummy cycle to elapse to ensure

that the device is fully powered up before attempting a valid

conversion. Likewise, if the device is kept in partial power-down

mode immediately after the supplies are applied, then initiate

two dummy cycles. The first dummy cycle must hold CS low until

after the 10th SCLK falling edge; in the second cycle, CS must be

brought high between the second and 10th SCLK falling edges

(see Figure 26).

Alternatively, if the device is placed into full power-down mode

when the supplies are applied, three dummy cycles must be

initiated. The first dummy cycle must hold CS low until after

the 10th SCLK falling edge; the second and third dummy cycles

place the device into full power-down mode (see Figure 28 and

the Modes of Operation section).

POWER vs. THROUGHPUT RATE

The power consumption of the AD7357 varies with the

throughput rate. When using very slow throughput rates and as

fast an SCLK frequency as possible, the various power-down

options can be used to make significant power savings. However,

the AD7357 quiescent current is low enough that even without

using the power-down options, there is a noticeable variation in

power consumption with sampling rate. This is true whether a

fixed SCLK value is used or if it is scaled with the sampling rate.

Figure 30 shows a plot of power vs. throughput rate when operating

in normal mode for a fixed maximum SCLK frequency and an

SCLK frequency that scales with the sampling rate. The internal

reference is used for Figure 30.

1000

2000

3000

4000

THROUGHPUT RATE (kSPS)

80MHz SCLK

VARIABLE SCLK

Figure 30. Total Power vs. Throughput Rate

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