Z89321 datasheet(33/40 Pages) ZILOG

33 / 40 page

Z89321/371/391

Zilog

16-Bit Digital Signal Processors

DS97DSP0100

P R E L I M I N A R Y

16-Bit General-Purpose Timer

The 13-bit counter/timer is available for general-purpose

use. When the counter counts down to the zero state, an

interrupt is received on INT2. If the counter is disabled,

EXT4 can be used as a general-purpose address. The

counting operation of the counter can be disabled by reset-

ting bit 14. Selection of the clock source allows the ability

to extend the counter value past the 13 bits available in the

control register. Use of the CODEC counter output can ex-

tend the counter to 26 bits (see Figure 33).

Note: Placing zeroes into the count value register does

not generate an interrupt. Therefore, it is possible to have

a single-pass option by loading the counter with zeroes

after the start of count.

The counter is defaulted to the enable state, but if it is not

needed, it can be disabled. However, once disabled, the

counter cannot be enabled unless a reset of the processor

is performed.

Example:

Figure 32. CODEC Stereo Mode Timing Diagram

64 bits transferred

int1_

fs1

fs0

sclk

txd

rxd

LD EXT, #%C008 ;1100 0000 0000 1000

; Enable Counter

; Enable Counting

; Clock Source = OSC/2

; Count Value = 1000 = 8

; Interrupt will occur every

16 clock cycles

Z89321 Datasheet(PDF) 33 Page - Zilog, Inc.