AD7923 datasheet(4/20 Pages) AD

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–4–

AD7923

REV. 0

TIMING SPECIFICATIONS1 (AV

DD = 2.7 V to 5.25 V, VDRIVE

AVDD, REFIN = 2.5 V, TA = TMIN to TMAX, unless otherwise noted.)

Limit at TMIN, TMAX AD7923

Parameter

AVDD = 3 V

AVDD = 5 V

Unit

Description

fSCLK

kHz min

MHz max

tCONVERT

¥ tSCLK

tQUIET

ns min

Minimum Quiet Time Required between

CS Rising

Edge and Start of Next Conversion

ns min

CS to SCLK Setup Time

ns max

Delay from

CS until DOUT Three-State Disabled

ns max

Data Access Time after SCLK Falling Edge

0.4

¥ tSCLK

0.4

¥ tSCLK

ns min

SCLK Low Pulsewidth

0.4

¥ tSCLK

0.4

¥ tSCLK

ns min

SCLK High Pulsewidth

ns min

SCLK to DOUT Valid Hold Time

15/45

15/35

ns min/max

SCLK Falling Edge to DOUT High Impedance

ns min

DIN Setup Time Prior to SCLK Falling Edge

t10

ns min

DIN Hold Time after SCLK Falling Edge

t11

ns min

Sixteenth SCLK Falling Edge to

CS High

t12

ms max

Power-Up Time from Full Power-Down/Auto

Shutdown Mode

NOTES

1Sample tested at 25

∞C to ensure compliance. All input signals are specified with tR = tF = 5 ns (10% to 90% of AVDD) and timed from a voltage level of 1.6 V.

See Figure 1. The 3 V operating range spans from 2.7 V to 3.6 V. The 5 V operating range spans from 4.75 V to 5.25 V.

2Mark/Space ratio for the SCLK input is 40/60 to 60/40.

3Measured with the load circuit of Figure 1 and defined as the time required for the output to cross 0.4 V or 0.7

¥ VDRIVE.

8 is derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 1. The measured number i s then extrapolated

back to remove the effects of charging or discharging the 50 pF capacitor. This means that the time, quoted in the timing characteristics t 8, is the true bus relinquish

time of the part and is independent of the bus loading.

Specifications subject to change without notice.

OUTPUT

50pF

200 A

IOH

200 A

IOL

1.6V

Figure 1. Load Circuit for Digital Output Timing Specifications

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