SSD1801Z datasheet(10/42 Pages) ETC

10 / 42 page

SSD1801 Series

Rev 1.1

01/2003

SOLOMON

PIN DESCRIPTIONS

D/ C

This pin is Data/ Command control pin. When the pin is pulled high, the data at D7-D0 is treated as display data.

When the pin is pulled low, the data at D7-D0 will be transferred to the command register.

W ( WR )

This pin is microprocessor interface input. When interfacing to a 6800-series microprocessor, this pin will be used

as R/W signal input. Read mode will be carried out when this pin is pulled high and write mode when low.

When interfacing to a 8080-microprocessor, this pin will be the WR input. Data write operation is initiated when

this pin is pulled low and the chip is selected.

This pin must be fixed to high or low in serial mode.

DVDD & AVDD

Digital and Analog Power supply pin.

DVSS & AVSS

Ground.

E( RD )

This pin is microprocessor interface input. When interfacing to a 6800-series microprocessor, this pin will be used

as the enable signal, E. Read/ Write operation is initiated when this pin is pulled high and the chip is selected.

When interfacing to a 8080-microprocessor, this pin receives the RD signal. Data read operation is initiated when

this pin is pulled low and the chip is selected.

This pin must be fixed to high or low in serial mode.

This pin is the chip select input.

D7-D0

These pins are the 8-bit bi-directional data bus to be connected to the microprocessor in parallel interface mode.

In 8-bit bus mode, D7 is the MSB while D0 is the LSB. In 4-bit bus mode, it is needed to transfer 4-bit data (through

D7-D4) by two times. The high order bits (for 8-bit mode D7-D4) are written before the low order bits (for 8-bit mode

D3-D0) in write transaction and low order bits (8-bit mode D3-D0) are read before the high order bits (8-bit mode D7-

D4) in read transaction. The D3-D0 pins must be fixed to high or low in 4-bit bus mode. After resets, SSD1801

considers first 4-bit data from MPU as the high order bits.

When serial mode is selected, D7 is the serial data input (SDA) and D6 is the serial clock input (SCK). D5-D0 must

be fixed to high or low in serial mode

VL6, VL5 , VL4, VL3, VL2

LCD driving voltages. They can be supplied externally or generated by the internal bias divider. They have the

following relationship:

VL6 > VL5 > VL4 > VL3 > VL2 > Vss

1:4 bias

1:5 bias (default)

VL5

3/4 * VL6

4/5 * VL6

VL4

2/4 * VL6

3/5 * VL6

VL3

2/4 * VL6

2/5 * VL6

VL2

1/4 * VL6

1/5 * VL6

VL6 is the most positive LCD driving voltage. It can be supplied externally or generated by the internal regulator. It is

recommended to add a capacitor between VL6 and Vss for external regulator.

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