V850ESLASHMA3 datasheet(18/226 Pages) NEC

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CHAPTER 2 REGISTER SET

User’s Manual U14559EJ3V1UM

2.2 System Registers

The system registers control the CPU status and hold information on interrupts.

System registers can be read or written by specifying the relevant system register number from the following list

using a system register load/store instruction (LDSR or STSR instruction).

Table 2-2. System Register Numbers

Operand Specifiability

No.

LDSR

Instruction

STSR

Instruction

Interrupt status saving register (EIPC)

Interrupt status saving register (EIPSW)

NMI status saving register (FEPC)

NMI status saving register (FEPSW)

Exception cause register (ECR)

Program status word (PSW)

6 to 15

(Numbers reserved for future function expansion (operation cannot be guaranteed if

accessed))

CALLT caller status saving register (CTPC)

CALLT caller status saving register (CTPSW)

Exception/debug trap status saving register (DBPC)

Note 1

Exception/debug trap status saving register (DBPSW)

Note 1

CALLT base pointer (CTBP)

Debug interface register (DIR)

Note 1

Breakpoint control registers 0 and 1 (BPC0, BPC1)

Note 2

Note 1

Program ID register (ASID)

Breakpoint address setting registers 0 and 1 (BPAV0, BPAV1)

Note 2

Note 1

Breakpoint address mask registers 0 and 1 (BPAM0, BPAM1)

Note 2

Note 1

Breakpoint data setting registers 0 and 1 (BPDV0, BPDV1)

Note 2

Note 1

Breakpoint data mask registers 0 and 1 (BPDM0, BPDM1)

Note 2

Note 1

28 to 31

(Numbers reserved for future function expansion (operation cannot be guaranteed if

accessed))

Notes 1.

These registers can be accessed only in the debug mode of type A and B products. Accessing these

registers in other product types is prohibited. If they are accessed, the operation is not guaranteed.

The actual register to be accessed is specified by the DIR.CS bit.

Caution When returning using the RETI instruction after setting bit 0 of EIPC, FEPC, or CTPC to 1 using

the LDSR instruction and servicing an interrupt, the value of bit 0 is ignored (because bit 0 of the

PC is fixed to 0). Therefore, be sure to set an even number (bit 0 = 0) when setting a value to

EIPC, FEPC, or CTPC.

Remark

O: Accessible

×: Inaccessible

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