V850ESLASHMA3 datasheet(39/226 Pages) NEC

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CHAPTER 4 ADDRESS SPACE

User’s Manual U14559EJ3V1UM

4.2 Addressing Mode

The CPU generates two types of addresses: instruction addresses used for instruction fetch and branch

operations; and operand addresses used for data access.

4.2.1 Instruction address

An instruction address is determined by the contents of the program counter (PC), and is automatically

incremented (+2) according to the number of bytes of an instruction to be fetched each time an instruction is executed.

When a branch instruction is executed, the branch destination address is loaded into the PC using one of the following

two addressing modes.

(1) Relative addressing (PC relative)

The signed 9- or 22-bit data of an instruction code (displacement: disp

×) is added to the value of the program

counter (PC). At this time, the displacement is treated as 2’s complement data with bits 8 and 21 serving as sign

bits (S).

This addressing is used for the JARL disp22, reg2, JR disp22, and Bcond disp9 instructions.

Figure 4-2. Relative Addressing (1/2)

(a) JARL disp22, reg2 instruction, JR disp22 instruction

0PC

000 00

Sign extension

disp22

Memory to be manipulated

0PC

000 00

V850E/MA3 Datasheet(PDF) 39 Page - NEC