AD7634BSTZ datasheet(18/33 Pages) AD

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Data Sheet

AD7634

Rev. B | Page 17 of 32

THEORY OF OPERATION

SW+

COMP

SW–

IN+

REF

REFGND

LSB

MSB

131,072C

65,536C

CONTROL

LOGIC

SWITCHES

CONTROL

BUSY

OUTPUT

CODE

CNVST

IN–

LSB

MSB

AGND

131,072C 65,536C

Figure 25. ADC Simplified Schematic

OVERVIEW

The AD7634 is a very fast, low power, precise, 18-bit ADC using

successive approximation capacitive digital-to-analog (CDAC)

architecture.

The AD7634 can be configured at any time for one of four input

ranges and conversion mode with inputs in parallel and serial

hardware modes or by a dedicated write-only, SPI-compatible

interface via a configuration register in serial software mode.

The AD7634 uses Analog Devices’ patented iCMOS high volt-

age process to accommodate 0 V to +5 V (10 V p-p), 0 V to

+10 V (20 V p-p), ±5 V (20 V p-p), and ±10 V (40 V p-p) input

ranges on the fully differential IN+ and IN− inputs without the

use of conventional thin films. Only one acquisition cycle, t8, is

required for the inputs to latch to the correct configuration. Reset-

ting or power cycling is not required for reconfiguring the ADC.

The AD7634 features different modes to optimize performance

according to the applications. It is capable of converting 670,000

samples per second (670 kSPS) in warp mode, 570 kSPS in normal

mode, and 450 kSPS in impulse mode.

The AD7634 provides the user with an on-chip, track-and-hold,

successive approximation ADC that does not exhibit any pipe-

line or latency, making it ideal for multiple, multiplexed channel

applications.

For unipolar input ranges, the AD7634 typically requires three

supplies: VCC, AVDD (which can supply DVDD), and OVDD

(which can be interfaced to either 5 V, 3.3 V, or 2.5 V digital logic).

For bipolar input ranges, the AD7634 requires the use of the

additional VEE supply.

The device is housed in a Pb-free, 48-lead LQFP or a 48-lead

tiny LFCSP (7 mm × 7 mm) that combine space savings with

flexibility. In addition, the AD7634 can be configured as either

a parallel or serial SPI-compatible interface.

CONVERTER OPERATION

The AD7634 is a successive approximation ADC based on a

charge redistribution DAC. Figure 25 shows the simplified

schematic of the ADC. The CDAC consists of two identical

arrays of 18 binary weighted capacitors, which are connected

to the two comparator inputs.

During the acquisition phase, terminals of the array tied to the

comparator’s input are connected to AGND via SW+ and SW−.

All independent switches are connected to the analog inputs. Thus,

the capacitor arrays are used as sampling capacitors and acquire

the analog signal on IN+ and IN− inputs. A conversion phase is

initiated once the acquisition phase is completed and the CNVST

input goes low. When the conversion phase begins, SW+ and SW−

are opened first. The two capacitor arrays are then disconnected

from the inputs and connected to the REFGND input. Therefore,

the differential voltage between the inputs (IN+ and IN−) captured

at the end of the acquisition phase is applied to the comparator

inputs, causing the comparator to become unbalanced. By switch-

ing each element of the capacitor array between REFGND and

REF, the comparator input varies by binary weighted voltage

steps (VREF/2, VREF/4 through VREF/ 262,144). The control logic

toggles these switches, starting with the MSB first, to bring the

comparator back into a balanced condition.

After the completion of this process, the control logic generates

the ADC output code and brings the BUSY output low.

MODES OF OPERATION

The AD7634 features three modes of operation: warp, normal,

and impulse. Each of these modes is more suitable to specific

applications. The mode is configured with the input pins, WARP

and IMPULSE, or via the configuration register. See Table 6 for

the pin details; see the Hardware Configuration section and the

Software Configuration section for programming the mode

selection with either pins or configuration register. Note that

when using the configuration register, the WARP and IMPULSE

inputs are don’t cares and should be tied to either high or low.

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