AD7904 datasheet(18/24 Pages) AD

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AD7904/AD7914/AD7924

REV. 0

better dynamic performance with a VDD of 5 V while still being

able to interface to 3 V processors. Care should be taken to

ensure VDRIVE does not exceed VDD by more than 0.3 V. (See

the Absolute Maximum Ratings section).

Reference

An external reference source should be used to supply the 2.5 V

reference to the AD7904/AD7914/AD7924. Errors in the refer-

ence source will result in gain errors in the AD7904/AD7914/

AD7924 transfer function and will add to the specified full-scale

errors of the part. A capacitor of at least 0.1

µF should be placed

on the REFIN pin. Suitable reference sources for the AD7904/

AD7914/AD7924 include the AD780, REF 193, and the AD1582.

If 2.5 V is applied to the REFIN pin, the analog input range can

either be 0 V to 2.5 V or 0 V to 5 V, depending on the setting of

the RANGE bit in the Control Register.

MODES OF OPERATION

The AD7904/AD7914/AD7924 have a number of different

modes of operation. These modes are designed to provide flex-

ible power management options. These options can be chosen

to optimize the power dissipation/throughput rate ratio for dif-

fering application requirements. The mode of operation of the

AD7904/AD7914/AD7924 is controlled by the power manage-

ment bits, PM1 and PM0, in the Control Register, as detailed in

Table III. When power supplies are first applied to the AD7904/

AD7914/AD7924, care should be taken to ensure that the part

is placed in the required mode of operation (see the Powering

Up the AD7904/AD7914/AD7924 section).

Normal Mode (PM1 = PM0 = 1)

This mode is intended for the fastest throughput rate performance

as the user does not have to worry about any power-up times

with the AD7904/AD7914/AD7924 remaining fully powered at

all times. Figure 11 shows the general diagram of the operation

of the AD7904/AD7914/AD7924 in this mode.

The conversion is initiated on the falling edge of

CS and the track

and hold will enter hold mode as described in the Serial Interface

section. The data presented to the AD7904/AD7914/AD7924 on

the DIN line during the first 12 clock cycles of the data transfer

are loaded into the Control Register (provided WRITE bit is set

to 1). The part will remain fully powered up in normal mode at

the end of the conversion as long as PM1 and PM0 are set to 1

in the write transfer during that same conversion. To ensure

continued operation in Normal Mode, PM1 and PM0 must both

be loaded with 1 on every data transfer, assuming a write opera-

tion is taking place. If the WRITE bit is set to 0, then the power

management bits will be left unchanged and the part will remain

in Normal Mode.

Sixteen serial clock cycles are required to complete the conver-

sion and access the conversion result. The track and hold will go

back into track on the fourteenth SCLK falling edge.

CS may

then idle high until the next conversion or may idle low until

sometime prior to the next conversion, (effectively idling

CS low).

Once a data transfer is complete (DOUT has returned to three-

state), another conversion can be initiated after the quiet time,

tQUIET, has elapsed by bringing CS low again.

SCLK

DOUT

DIN

2 LEADING ZEROS + 2 CHANNEL IDENTIFIER BITS

+ CONVERSION RESULT

DATA IN TO CONTROL REGISTER

NOTE: CONTROL REGISTER DATA IS LOADED ON FIRST 12 SCLK CYCLES

Figure 11. Normal Mode Operation

Full Shutdown (PM1 = 1, PM0 = 0)

In this mode, all internal circuitry on the AD7904/AD7914/

AD7924 is powered down. The part retains information in the

Control Register during full shutdown. The AD7904/AD7914/

AD7924 remains in full shutdown until the power management

bits in the Control Register, PM1 and PM0, are changed.

If a write to the Control Register occurs while the part is in Full

Shutdown, with the power management bits changed to PM0 =

PM1 = 1, Normal mode, the part will begin to power up on the

CS rising edge. The track and hold that was in hold while the

part was in Full Shutdown will return to track on the fourteenth

SCLK falling edge.

To ensure that the part is fully powered up, tPOWER UP (t12) should

have elapsed before the next

CS falling edge. Figure 12 shows

the general diagram for this sequence.

Auto Shutdown (PM1 = 0, PM0 = 1)

In this mode, the AD7904/AD7914/AD7924 automatically enters

shutdown at the end of each conversion when the control register

is updated. When the part is in shutdown, the track and hold is in

hold mode. Figure 13 shows the general diagram of the operation

of the AD7904/AD7914/AD7924 in this mode. In shutdown mode

all internal circuitry on the AD7904/AD7914/AD7924 is

powered down. The part retains information in the Control

remains in shutdown until the next

CS falling edge it receives.

On this

CS falling edge the track and hold that was in hold while

the part was in shutdown will return to track. Wake-up time

from auto shutdown is 1

µs maximum, and the user should

ensure that 1

µs has elapsed before attempting a valid conver-

sion. When running the AD7904/AD7914/AD7924 with a

20 MHz clock, one 16 SCLK dummy cycle should be sufficient

to ensure the part is fully powered up. During this dummy cycle

the contents of the Control Register should remain unchanged,

therefore the WRITE bit should be 0 on the DIN line. This

dummy cycle effectively halves the throughput rate of the part,

with every other conversion result being valid. In this mode the

power consumption of the part is greatly reduced with the part

entering shutdown at the end of each conversion. When the

Control Register is programmed to move into auto shutdown, it

does so at the end of the conversion. The user can move the ADC

in and out of the low power state by controlling the

CS signal.

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