AD7904 datasheet(21/24 Pages) AD

21 / 24 page

AD7904/AD7914/AD7924

–21–

REV. 0

Figure 15 shows the maximum power versus throughput rate

when using the Auto Shutdown mode with 5 V and 3 V supplies.

THROUGHPUT – kSPS

100

200

300

0.1

0.01

150

250

350

VDD = 5V

VDD = 3V

Figure 15. AD7924 Power vs. Throughput Rate

SERIAL INTERFACE

Figures 16, 17, and 18 show the detailed timing diagrams for

serial interfacing to the AD7904, AD7914, and AD7924,

respectively. The serial clock provides the conversion clock and

also controls the transfer of information to and from the

AD7904/AD7914/AD7924 during each conversion.

The

CS signal initiates the data transfer and conversion process.

The falling edge of

CS puts the track and hold into hold mode,

takes the bus out of three-state and the analog input is sampled

at this point. The conversion is also initiated at this point and

will require 16 SCLK cycles to complete. The track and hold

will go back into track on the fourteenth SCLK falling edge as

shown in Figures 16, 17, and 18 at Point B. On the sixteenth

SCLK falling edge, the DOUT line will go back into three-state.

If the rising edge of

CS occurs before 16 SCLKs have elapsed,

the conversion will be terminated, the DOUT line will go back

into three-state, and the Control Register will not be updated;

otherwise DOUT returns to three-state on the sixteenth SCLK

falling edge as shown in Figures 16, 17, and 18.

SCLK

DOUT

DIN

t11

tQUIET

tCONVERT

345

THREE-

STATE

ZERO

ADD1

ADD0

DB7

DB6

DB0

ZERO

THREE-

STATE

4 TRAILING ZEROS

2 IDENTIFICATION

BITS

t10

ZERO

WRITE

SEQ1

DONTC

ADD1

ADD0

CODING

DONTC

Figure 16. AD7904 Serial Interface Timing Diagram

SCLK

DOUT

DIN

t11

tCONVERT

345

THREE-

STATE

ZERO

ADD1

ADD0

DB9

DB8

DB2

DB1

DB0

ZERO

THREE-

STATE

2 TRAILING ZEROS

2 IDENTIFICATION

BITS

t10

ZERO

WRITE

SEQ1

DONTC

ADD1

ADD0

CODING

DONTC

tQUIET

Figure 17. AD7914 Serial Interface Timing Diagram

SCLK

DOUT

DIN

t11

tCONVERT

345

THREE-

STATE

ZERO

ADD1

ADD0

DB11

DB10

DB4

DB3

DB2

DB1

DB0

THREE-

STATE

2 IDENTIFICATION

BITS

t10

ZERO

WRITE

SEQ1

DONTC

ADD1

ADD0

CODING

DONTC

tQUIET

Figure 18. AD7924 Serial Interface Timing Diagram

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