AD5392BCP-3 datasheet(13/44 Pages) AD

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AD5390/AD5391/AD5392

Rev. A | Page 13 of 44

TIMING CHARACTERISTICS: I2C SERIAL INTERFACE

Guaranteed by design and characterization, not production tested. DVDD = 2.7 V to 5.5 V; AVDD = 2.7 V to 5.5 V; AGND = DGND = 0 V.

All specifications TMIN to TMAX, unless otherwise noted.

Table 7.

Parameter1

Limit at TMIN, TMAX

Unit

Description

FSCL

400

kHz max

SCL clock frequency

2.5

µs min

SCL cycle time

0.6

µs min

tHIGH, SCL high time

1.3

µs min

tLOW, SCL low time

0.6

µs min

tHD, STA, start/repeated start condition hold time

100

ns min

tSU, DAT, data setup time

t62

0.9

µs max

tHD, DAT data hold time

µs min

tHD, DAT data hold time

0.6

µs min

tSU, STA setup time for repeated start

0.6

µs min

tSU, STO stop condition setup time

1.3

µs min

tBUF, bus free time between a stop and a start condition

t10

300

ns max

tF, fall time of SDA when transmitting

ns min

tR, rise time of SCL and SDA when receiving (CMOS-compatible)

t11

300

ns max

tF, fall time of SDA when transmitting

ns min

tF, fall time of SDA when receiving (CMOS-compatible)

300

ns max

tF, fall time of SCL and SDA when receiving

20 + 0.1 CB

ns min

tF, fall time of SCL and SDA when transmitting

CB3

400

pF max

Capacitive load for each bus line

1 See F

igure 6

2 A master device must provide a hold time of at least 300 ns for the SDA signal (referred to the VIH MIN of the SCL signal)

to bridge the undefined region of SCL’s falling edge.

3 CB is the total capacitance of one bus line in pF; tR and tF measured between 0.3 DVDD and 0.7 DVDD.

SCL

SDA

START

CONDITION

REPEATED

START

CONDITION

STOP

CONDITION

t10

t11

Figure 6. I2C Interface Timing Diagram

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