AD7691 datasheet(19/29 Pages) AD

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AD7691

Data Sheet

Rev. E | Page 18 of 28

CS MODE, 3-WIRE WITHOUT BUSY INDICATOR

This mode is usually used when a single AD7691 is connected

to an SPI-compatible digital host. The connection diagram is

shown in Figure 35, and the corresponding timing is given in

Figure 36.

With SDI tied to VIO, a rising edge on CNV initiates a

conversion, selects the CS mode, and forces SDO to high

impedance. Once a conversion is initiated, it continues until

completion irrespective of the state of CNV. This can be useful,

for instance, to bring CNV low to select other SPI devices, such

as analog multiplexers, but CNV must be returned high before

the minimum conversion time elapses and then held high for

the maximum possible conversion time to avoid the generation

of the busy signal indicator. When the conversion is complete,

the AD7691 enters the acquisition phase and powers down.

When CNV goes low, the MSB is output onto SDO. The

remaining data bits are clocked by subsequent SCK falling

edges. The data is valid on both SCK edges. Although the rising

edge can be used to capture the data, a digital host using the

SCK falling edge can allow a faster reading rate, provided it has

an acceptable hold time. After the 18th SCK falling edge, or

when CNV goes high, whichever occurs first, SDO returns to

high impedance.

Figure 35. 3-Wire CS Mode Without Busy Indicator

Connection Diagram (SDI High)

Figure 36. 3-Wire CS Mode Without Busy Indicator Serial Interface Timing (SDI High)

CNV

SCK

SDO

SDI

DATA IN

CLK

CONVERT

VIO

DIGITAL HOST

AD7691

SDO

D17

D16

D15

tDIS

SCK

123

tSCK

tSCKL

tSCKH

tHSDO

tDSDO

CNV

CONVERSION

ACQUISITION

tCONV

tCYC

ACQUISITION

SDI = 1

tCNVH

tACQ

tEN

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