Data Sheet

AD7796/AD7797

Rev. B | Page 13 of 24

Table 13. Operating Modes

MD2

MD1

MD0

Mode

0

0

0

Continuous Conversion Mode (default). In continuous conversion mode, the ADC continuously performs

conversions and places the result in the data register. RDY goes low when a conversion is complete. The user can

read these conversions by placing the device in continuous read mode, whereby the conversions are automatically

placed on the DOUT line when SCLK pulses are applied. Alternatively, the user can instruct the ADC to output the

conversion by writing to the communication register. After a power-on, channel change, or write to the mode or

0

0

1

Single Conversion Mode. When single conversion mode is selected, the ADC powers up and performs a single

conversion. The oscillator requires 1 ms to power up and settle. The ADC then performs the conversion, which takes

down mode. The conversion remains in the data register and RDY remains active (low) until the data is read or

another conversion is performed.

0

1

0

Idle Mode. In idle mode, the ADC filter and modulator are held in a reset state although the modulator clocks are

still provided.

0

1

1

Power-Down Mode. In power-down mode, all the AD7796/AD7797 circuitry is powered down, including the

burnout currents and CLKOUT circuitry.

1

0

0

Internal Zero-Scale Calibration. An internal short is automatically connected to the channel. A calibration takes

two conversion cycles to complete. RDY goes high when the calibration is initiated and returns low when the

calibration is complete. The ADC is placed in idle mode following a calibration. The measured offset coefficient is

placed in the offset register.

1

0

1

Reserved.

1

1

0

System Zero-Scale Calibration. Users should connect the system zero-scale input to the channel input pins.

A system offset calibration takes two conversion cycles to complete. RDY goes high when the calibration is

initiated and returns low when the calibration is complete. The ADC is placed in idle mode following a calibration.

The measured offset coefficient is placed in the offset register.

1

1

1

System Full-Scale Calibration. Users should connect the system full-scale input to the channel input pins.

A calibration takes two conversion cycles to complete. RDY goes high when the calibration is initiated and returns

low when the calibration is complete. The ADC is placed in idle mode following a calibration. The measured full-

scale coefficient is placed in the full-scale register.

Table 14. Update Rates Available

FS3

FS2

FS1

FS0

Rejection at 50 Hz/60 Hz (Internal Clock)

0

0

0

0

X

X

0

0

0

1

X

X

0

0

1

0

X

X

0

0

1

1

123

16

0

1

0

0

62

32

0

1

0

1

50

40

0

1

1

0

X

X

0

1

1

1

33.2

60

1

0

0

0

X

X

1

0

0

1

16.7

120

80 dB (50 Hz only)

1

0

1

0

16.7

120

65 dB (50 Hz and 60 Hz)

1

0

1

1

12.5

160

66 dB (50 Hz and 60 Hz)

1

1

0

0

10

200

69 dB (50 Hz and 60 Hz)

1

1

0

1

8.33

240

70 dB (50 Hz and 60 Hz)

1

1

1

0

6.25

320

72 dB (50 Hz and 60 Hz)

1

1

1

1

4.17

480

74 dB (50 Hz and 60 Hz)