Applications Information

SERIAL DATA ENTRY INTO THE DS8906

Serial information entry into the DS8906 is enabled by a low

level on the ENABLE input One binary bit is then accepted

from the DATA input with each positive transition of the

CLOCK input The CLOCK input must be low for the speci-

fied time preceding and following the negative transition of

the ENABLE input

The first 2 bits accepted following the negative transition of

the ENABLE input are interpreted as address If these ad-

dress bits are

not 11 no further information will be accept-

ed from the DATA inputs and the internal data latches

will

not be changed when ENABLE returns high

If these first 2 bits

are 11 then all succeeding bits are ac-

cepted as data and are shifted successively into the inter-

nal shift register as long as ENABLE remains low

Any

data bits preceding the 20th to last bit will be shifted

out and are thus irrelevant Data bits are counted as any

bits following 2 valid (11) address bits with the ENABLE

low

When the ENABLE input returns high any further serial data

input is inhibited

Upon this positive transition of the

ENABLE the data in the internal shift register is transferred

into the internal data latches

Note that until this time the states of the internal data latch-

es have remained unchanged

These data bits are interpreted as follows

DATA BIT POSITION

DATA INTERPRETATION

Last

Bit 20 Output (Pin 2)

2nd to Last

Bit 19 Output (Pin 1)

3rd to Last

Bit 18 Output (FMAM) (Pin 20)

4th to Last

Bit 17 Output (Pin 19)

5th to Last

Bit 16 Output (Pin 18)

6th to Last

Bit 15 Output (Pin 17)

7th to Last

MSB of N

8th to Last

9th to Last

10th to Last

11th to Last

12th to Last

13th to Last

d

N

14th to Last

15th to Last

16th to Last

17th to Last

18th to Last

19th to Last

20th to Last

LSB of N

-

Note

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